# US 10,321,581 B2 · Single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,321,581 B2
- Document ID: US10321581B2
- Status: Granted
- Kind: B2
- Application number: 15/773,772
- Filed: 2016-11-23
- Published: 2018-11-08
- Granted: 2019-06-11
- Earliest claimed: 2015-11-06
- Assignees: Richview Electronics Co., Ltd.
- Applicants: Richview Electronics Co., Ltd.
- Inventors: Siping Bai; Xianglan Wu; Zhijian Wang; Zhigang Yang; Jinqiang Zhang
- Web page: https://patentgrep.com/patent/US10321581B2

## CPC

- H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers}
- C23C 14/48: Ion implantation
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/105: {by conversion of non-conductive material on or in the support into conductive material, e.g. by using an energy beam}
- H05K 3/42: Plated through-holes {or plated via connections}
- H05K 3/422: {characterised by electroless plating method; pretreatment therefor}
- H05K 3/423: {characterised by electroplating method}
- H05K 3/427: {initial plating of through-holes in metal-clad substrates}
- H05K 3/048: {using a lift-off resist pattern or a release layer pattern}
- H05K 3/06: the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)}
- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H05K 3/421: {Blind plated via connections (H05K3/422, H05K3/423 and H05K3/425 take precedence)}
- H05K 3/426: {initial plating of through-holes in substrates without metal}
- H05K 3/4617: {characterized by laminating only or mainly similar single-sided circuit boards}
- H05K 2201/0355: Metal foils
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2203/0565: Resist used only for applying catalyst, not for plating itself
- H05K 2203/0769: Dissolving insulating materials, e.g. coatings, not used for developing resist after exposure
- H05K 2203/092: Particle beam, e.g. using an electron beam or an ion beam
- H05K 2203/1423: Applying catalyst before etching, e.g. plating catalyst in holes before etching circuit
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)

## Abstract

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

## Claims

### Claim 1

A method for manufacturing single-layer circuit board, the method comprising:
drilling a hole on a substrate, the hole comprises a blind hole and/or a through hole;
on a surface of said substrate, forming a photoresist layer having a circuit negative image;
forming a conductive seed layer on the surface of said substrate and a hole wall of said hole; and
removing said photoresist layer, to form a circuit pattern on the surface of said substrate,
wherein forming a conductive seed layer comprises, implanting a conductive material below the surface of said substrate and below the hole wall of said hole via ion implantation, to form an ion implantation layer as at least part of said conductive seed layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the conductive seed layer further comprises, depositing a conductive material above said ion implantation layer via plasma deposition, to form plasma deposition layer, said plasma deposition layer and said ion implantation layer constitute said conductive seed layer, wherein during said plasma deposition, the ions of said conductive material gain energy of 1-1000 eV, form plasma deposition layer in a thickness of 1-10000 nm.

### Claim 3 (depends on 1)

The method of claim 1, wherein after forming the conductive seed layer and before removing said photoresist layer, said methods further comprises: via one or more of electroplating, chemical plating, vacuum evaporation, sputtering, utilizing one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloy thereof, forming a conductor thickening layer on said conductive seed layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein during said ion implantation, the ions of said conductive material gain energy of 1-1000 keV, are implanted below the surface of said substrate and below the hole wall of said hole for a depth of 1-500 nm, and form a steady doping structure with said substrate.