# US 10,321,575 B2 · Integrated circuit (IC) module comprising an integrated circuit (IC) package and an interposer with embedded passive components > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,321,575 B2 - Document ID: US10321575B2 - Status: Granted - Kind: B2 - Application number: 14/842,403 - Filed: 2015-09-01 - Published: 2017-03-02 - Granted: 2019-06-11 - Earliest claimed: 2015-09-01 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Yue Li; Charles David Paynter; Ryan David Lane; Ruey Kae Zang - Web page: https://patentgrep.com/patent/US10321575B2 ## CPC - H05K 1/186: {manufactured by mounting on or connecting to patterned circuits before or during embedding} - H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass} - H05K 1/0313: {Organic insulating material} - H05K 1/113: {Via provided in pad; Pad over filled via} - H05K 1/114: {Pad being close to via, but not surrounding the via} - H10W 44/00: Electrical arrangements for controlling or matching impedance - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/01: Manufacture or treatment - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 2201/10015: Non-printed capacitor - H05K 2201/1003: Non-printed inductor - H10W 70/68: Shapes or dispositions thereof - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer. ## Claims ### Claim 1 A device comprising: a die; a substrate coupled to the die; and an interposer coupled to the substrate such that the die is located externally of the interposer, the interposer comprising: an encapsulation layer formed entirely by a single layer, the encapsulation layer comprising a first outer surface and a second outer surface, wherein the second outer surface is opposite to the first outer surface, the first outer surface of the encapsulation layer defines a first interposer outer surface, and the second outer surface of the encapsulation layer defines a second interposer outer surface; at least one via extending through the entirety of the encapsulation layer; a first passive component located externally of the die, the first passive component at least partially embedded in the encapsulation layer such that the first passive component is co-planar to the at least one via that extends through the entirety of the encapsulation layer, wherein a surface of the first passive component is co-planar to the first outer surface of the encapsulation layer, wherein the first passive component is configured such that an electrical signal travels between the first outer surface of the encapsulation layer and the second outer surface of the encapsulation layer, through the first passive component; a second passive component located externally of the die, the second passive component at least partially embedded in the encapsulation layer such that the second passive component is co-planar to the at least one via that extends through the entirety of the encapsulation layer, wherein the first passive component and the second passive component are located in the encapsulation layer such that the first passive component and the second passive component are offset towards the first outer surface of the encapsulation layer; and plurality of interconnects at least partially formed in the encapsulation layer, wherein at least one interconnect from the plurality of interconnects is coupled to the first passive component and wherein at least one other interconnect from the plurality of interconnects is coupled to the second passive component; and a plurality of first solder interconnects coupled to the plurality of interconnects. ### Claim 2 (depends on 1) The device of claim 1, wherein the encapsulation layer comprises an E-glass, a mold and/or an epoxy fill. ### Claim 3 (depends on 1) The device of claim 1, wherein the encapsulation layer comprises a photo litho-patternable layer. ### Claim 4 (depends on 1) The device of claim 1, further comprising: a plurality of second solder interconnects coupled to the interposer, wherein at least one solder interconnect from the plurality of second solder interconnects is coupled to the first passive component, and wherein at least one other solder interconnect from the plurality of second solder interconnects is coupled to the second passive component. ### Claim 5 (depends on 1) The device of claim 1, further comprising a pad coupled to the first passive component, wherein at least one solder interconnect from the second solder interconnect is coupled to the pad. ### Claim 6 (depends on 1) The device of claim 1, wherein the interposer is a fan out interposer comprising: a first portion comprising a plurality of first interconnects comprising a first minimum pitch; and a second portion comprising a plurality of second interconnects comprising a second minimum pitch. ### Claim 7 (depends on 6) The device of claim 6, wherein the second minimum pitch is less than the first minimum pitch. ### Claim 8 (depends on 1) The device of claim 1, further comprising an inductor formed by a plurality of first interconnects. ### Claim 9 (depends on 1) The device of claim 1, wherein the first passive component comprises a capacitor or an inductor. ### Claim 10 (depends on 1) The device of claim 1, wherein the first passive component is part of an electronic voltage regulator (EVR). ### Claim 11 (depends on 1) The device of claim 1, wherein the device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle, and further including the device. ### Claim 12 A device comprising: an integrated circuit (IC) package; a plurality of first solder interconnects coupled to the IC package; an interposer coupled to the IC package through the plurality of first solder interconnects such that the IC package is located externally of the interposer, the interposer comprising: an encapsulation layer formed entirely by a single layer, the encapsulation layer comprising a first outer surface and a second outer surface, wherein the second outer surface is opposite to the first outer surface, the first outer surface of the encapsulation layer defines a first interposer outer surface, and the second outer surface of the encapsulation layer defines a second interposer outer surface; at least one via extending through the entirety of the encapsulation layer; a first passive component at least partially embedded in the encapsulation layer such that the first passive component is co-planar to the at least one via that extends through the entirety of the encapsulation layer, wherein a surface of the first passive component is co-planar to the first outer surface of the encapsulation layer, wherein the first passive component is configured such that an electrical signal travels between the first outer surface of the encapsulation layer and the second outer surface of the encapsulation layer, through the first passive component; a second passive component at least partially embedded in the encapsulation layer such that the second passive component is co-planar to the at least one via that extends through the entirety of the encapsulation layer, wherein the first passive component and the second passive component are located in the encapsulation layer such that the first passive component and the second passive component are offset towards the first outer surface of the encapsulation layer; a plurality of interconnects coupled to the plurality of first solder interconnects, wherein the plurality of interconnects is at least partially formed in the encapsulation layer; wherein at least one interconnect from the plurality of interconnects is coupled to the first passive component, and wherein at least one other interconnect from the plurality of interconnects is coupled to the second passive component; a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. ### Claim 13 (depends on 12) The device of claim 12, wherein the encapsulation layer comprises an E-glass, a mold and/or an epoxy fill. ### Claim 14 (depends on 12) The device of claim 12, wherein the encapsulation layer comprises a photo litho-patternable layer. ### Claim 15 (depends on 12) The device of claim 12, wherein the interposer further comprises an inductor formed by a plurality of first interconnects. ### Claim 16 (depends on 12) The device of claim 12, further comprising: wherein at least one second solder interconnect from the plurality of second solder interconnects is coupled to the first passive component, and wherein at least one other solder interconnect from the plurality of second solder interconnects is coupled to the second passive component. ### Claim 17 (depends on 12) The device of claim 12, wherein the interposer is a fan out interposer comprising: a first portion comprising a plurality of first interconnects comprising a first minimum pitch; and a second portion comprising a plurality of second interconnects comprising a second minimum pitch. ### Claim 18 (depends on 12) The device of claim 12, wherein the first passive component comprises a capacitor or an inductor. ### Claim 19 (depends on 12) The device of claim 12, wherein the device is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle, and further including the device. ### Claim 20 (depends on 12) The device of claim 12, wherein the integrated circuit (IC) package comprises a die and a package substrate. ### Claim 21 (depends on 20) The device of claim 20, wherein the integrated circuit (IC) package further comprises another encapsulation layer. ### Claim 22 (depends on 12) The device of claim 12, wherein the surface of the first passive component faces the PCB, and the surface of the first passive component is co-planar to a surface of the encapsulation layer that faces the PCB. ### Claim 23 (depends on 12) The device of claim 12, wherein the first passive component comprises a height that is similar to a thickness of the encapsulation layer. ### Claim 24 (depends on 12) The device of claim 12, wherein the interposer comprises a thickness that is in a range of about 130-270 micrometers (μm). ### Claim 25 (depends on 12) The device of claim 12, wherein the interposer comprises a thickness that is in a range of about 130-170 micrometers (μm), and the first passive component comprises a thickness that is less than 100 micrometers (μm). ### Claim 26 (depends on 12) The device of claim 12, wherein the interposer comprises a thickness that is in a range of about 140-270 micrometers (μm), and the first passive component comprises a thickness that is in a range of about 110-150 micrometers (μm).