# US 10,321,163 B2 · High definition VP8 decoder > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,321,163 B2 - Document ID: US10321163B2 - Status: Granted - Kind: B2 - Application number: 15/646,258 - Filed: 2017-07-11 - Published: 2017-10-26 - Granted: 2019-06-11 - Earliest claimed: 2013-06-05 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Mihir Narendra Mody; Chaitanya S Ghone; Joseph Meehan - Web page: https://patentgrep.com/patent/US10321163B2 ## CPC - H04N 19/86: involving reduction of coding artifacts, e.g. of blockiness - H04N 19/42: characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) - H04N 19/44: Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder - H04N 19/82: involving filtering within a prediction loop - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation VP6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non-exact, approximate deblocking loop filter is implemented. ## Claims ### Claim 1 A video decoding system comprising: one or more processors configured to: perform entropy decoding in a frame level pipelined manner on a bitstream representing encoded video data to produce a first output; perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output to produce a second output; perform deblocking filtering on an input that includes the second output in a row level pipelined manner using a non-exact approximate loop filter to produce a third output; apply a fading compensation operation in a row level pipelined manner to the third output to produce a fourth output; apply a motion compensation operation in a row level pipelined manner to the fourth output to produce a fifth output; combine the fifth output with the second output by a feedback path; and output a decoded video output based on the third output. ### Claim 2 (depends on 1) The video decoding system of claim 1, wherein: the one or more processors comprises a first processor and a second processor; performing entropy decoding is performed by the first processor; and performing at least one of the inverse quantization operation or the inverse frequency transform operation is performed by the second processor. ### Claim 3 (depends on 2) The video decoding system of claim 2, wherein the second processor is a digital signal processor. ### Claim 4 (depends on 2) The video decoding system of claim 2, wherein the first processor is an embedded digital processor. ### Claim 5 (depends on 1) The video decoding system of claim 1, wherein the first output includes symbols recovered from the bitstream. ### Claim 6 An electronic device comprising: a display device; and one or more processors configured to: perform entropy decoding in a frame level pipelined manner on a bitstream representing encoded video data to produce a first output; perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output to produce a second output; perform deblocking filtering on an input that includes the second output in a row level pipelined manner using a non-exact approximate loop filter to produce a third output; apply a fading compensation operation in a row level pipelined manner to the third output to produce a fourth output; apply a motion compensation operation in a row level pipelined manner to the fourth output to produce a fifth output; combine the fifth output with the second output by a feedback path; produce a decoded video output based on the third input; and cause the decoded video output to be displayed on the display device. ### Claim 7 (depends on 6) The electronic device of claim 6, comprising: a memory storing program instructions; wherein the one or more processors are configured to execute the program instructions to: execute an entropy decoder routine to perform the entropy decoding; execute a numerical calculation routine to perform at least one of the inverse quantization operation or the inverse frequency transform operation; execute a deblocking filtering routine to perform the deblocking filtering; execute a fading compensation routine to perform the fading compensation operation; and execute a motion compensation routine to perform the motion compensation operation. ### Claim 8 (depends on 6) The video decoding system of claim 6, wherein: the one or more processors comprises a first processor and a second processor; performing entropy decoding is performed by the first processor; and performing at least one of the inverse quantization operation or the inverse frequency transform operation is performed by the second processor. ### Claim 9 (depends on 8) The video decoding system of claim 8, wherein the second processor is a digital signal processor. ### Claim 10 (depends on 8) The video decoding system of claim 8, wherein the first processor is an embedded digital processor. ### Claim 11 (depends on 6) The video decoding system of claim 6, wherein the first output includes symbols recovered from the bitstream. ### Claim 12 A video decoding system comprising: one or more processors configured to: perform entropy decoding in a frame level pipelined manner on a bitstream representing encoded video data to produce a first output; perform at least one of an inverse quantization operation or an inverse frequency transform operation on the first output to produce a second output; perform deblocking filtering on an input that includes the second output using a non-exact approximate loop filter to produce a third output; apply a fading compensation operation in a row level pipelined manner to the third output to produce a fourth output; apply a motion compensation operation to the fourth output to produce a fifth output; combine the fifth output with the second output by a feedback path; and output a decoded video output based on the third output; wherein the one or more processors comprises a first processor that is an embedded digital processor and a second processor that is a digital signal processor, performing entropy decoding is performed by the first processor, performing at least one of the inverse quantization operation or the inverse frequency transform operation is performed by the second processor; and wherein each of performing at least one of the inverse quantization operation or the inverse frequency transform operation, performing deblocking filtering, and applying the motion compensation operation are performed in a row level pipelined manner. ### Claim 13 (depends on 12) The video decoding system of claim 12, wherein the first output includes symbols recovered from the bitstream.