# US 10,321,079 B2 · Solid-state imaging apparatus having multiple structures to reduce the apparatus size, manufacturing method of the same, and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,321,079 B2 - Document ID: US10321079B2 - Status: Granted - Kind: B2 - Application number: 15/572,573 - Filed: 2016-05-02 - Published: 2018-05-31 - Granted: 2019-06-11 - Earliest claimed: 2015-05-15 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Shinji Miyazawa - Web page: https://patentgrep.com/patent/US10321079B2 ## CPC - H04N 25/767: Horizontal readout lines, multiplexers or registers - H04N 23/54: Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils - H04N 23/57: Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub} - H10F 39/018: {of hybrid image sensors} - H10F 39/8053: {Colour filters} - H10F 39/809: {of hybrid image sensors} - H10F 39/811: {Interconnections} - H10P 14/40: of conductive or resistive materials - H10W 20/01: {Manufacture or treatment} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias} - H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes} - H10F 39/182: {Colour image sensors} - H10F 39/199: {Back-illuminated image sensors} - H10F 39/804: {Containers or encapsulations} - H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/879: {Bump connectors and bond wires} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to a solid-state imaging apparatus, a manufacturing method of the same and an electronic device which can make an apparatus size further smaller. A solid-state imaging apparatus includes: a laminate of a first structure in which a pixel array unit in which pixels that perform photoelectric conversion are two-dimensionally arranged is formed and a second structure in which an output circuit unit configured to output pixel signals output from the pixels to an outside of an apparatus is formed. The output circuit unit, a first through hole via which penetrates through a semiconductor substrate constituting part of the second structure, and an external terminal for signal output connected to the outside of the apparatus are disposed below the pixel array unit of the first structure. The present disclosure can be applied, for example, to a solid-state imaging apparatus or the like. ## Claims ### Claim 1 A solid-state imaging apparatus comprising: a first structure including: a first semiconductor substrate including a pixel array unit, the pixel array unit including pixels that perform photoelectric conversion, the pixels being two-dimensionally arranged; a first multilayer wiring layer, wherein the first semiconductor substrate is on the first multilayer wiring layer; and a first bonding layer, wherein the first multilayer wiring layer is on the first bonding layer, and the first bonding layer includes one or more of an oxide, a nitride material, or carbon; a glass substrate bonded to the first semiconductor substrate; a second structure including: a second semiconductor substrate; and a second multilayer wiring layer on the second semiconductor substrate, wherein the second multilayer wiring layer includes a second bonding section, and wherein the second bonding section includes one or more of an oxide, a nitride material, or carbon; and a second bonding layer on the second multilayer wiring layer, wherein the second bonding layer includes one or more of an oxide, a nitride material, or carbon, wherein the second structure includes a signal processing circuit, an input circuit to receive a predetermined signal from an external device, and an output circuit to output pixel signals from the pixels to the external device, wherein the first multilayer wiring layer and the second multilayer wiring layer are between the first semiconductor substrate and the second semiconductor substrate, and wherein the first structure is directly bonded to the second structure via the first bonding layer and the second bonding layer; an output unit including: a first through hole that penetrates through the second semiconductor substrate; and a first terminal on the second semiconductor substrate that electrically connects the output circuit to the external device via the first through hole; and an input unit including: a second through hole that penetrates through the second semiconductor substrate; and a second terminal on the second semiconductor substrate that electrically connects the input circuit to the external device via the second through hole, wherein the output unit and the input unit are disposed within an area of the pixel array unit of the first structure in a plan view. ### Claim 2 A solid-state imaging apparatus comprising: a laminated structure including: a first substrate including a pixel layer and a first wiring layer electrically connected to one another, the pixel layer including a pixel array unit with pixels for performing photoelectric conversion, the pixels being two-dimensionally arranged in the pixel layer, wherein the first substrate includes a first bonding layer, and wherein the first bonding layer includes one or more of an oxide, a nitride material, or carbon; and a second substrate including: a second wiring layer including at least one output circuit to output pixel signals from the pixels; and a second bonding layer, wherein the second bonding layer includes one or more of an oxide, a nitride material, or carbon; a connection layer including a first through hole that penetrates through the connection layer to the at least one output circuit; and a first terminal to electrically connect the at least one output circuit to an external device via the first through hole, wherein the first wiring layer and the second wiring layer are between the pixel layer and the connection layer, and wherein the first substrate is directly bonded to the second substrate via the first bonding layer and the second bonding layer. ### Claim 3 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein, in the first substrate, at least part of a drive unit to drive the pixels is formed around the pixel array unit as a pixel peripheral circuit region, and wherein the at least one output circuit is a plurality of output circuits, part of the plurality of output circuits being disposed on a side of the pixel peripheral circuit region furthest from a light-incident side of the first substrate. ### Claim 4 (depends on 3) The solid-state imaging apparatus according to claim 3, wherein each of the plurality of output circuits has a corresponding first terminal electrically connected thereto. ### Claim 5 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the first terminal is a solder ball. ### Claim 6 (depends on 5) The solid-state imaging apparatus according to claim 5, wherein the solder ball is in the first through hole. ### Claim 7 (depends on 5) The solid-state imaging apparatus according to claim 5, wherein the solder ball is adjacent to the first through hole and electrically connected to the first through hole via a rewiring. ### Claim 8 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the first terminal is a rewiring. ### Claim 9 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the at least one output circuit is disposed in a line. ### Claim 10 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the at least one output circuit is integrated with the first terminal for signal output. ### Claim 11 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the second wiring layer includes at least one input circuit to receive a predetermined signal from the external device, and wherein the at least one input circuit is disposed on a side of the pixel array unit furthest from a light-incident side and the at least one input circuit is electrically connected to a second terminal via a second through hole that penetrates through the connection layer. ### Claim 12 (depends on 11) The solid-state imaging apparatus according to claim 11, wherein, in the first substrate, at least part of a drive unit to drive the pixels is formed around the pixel array unit as a pixel peripheral circuit region, and wherein the at least one input circuit is a plurality of input circuits, part of the plurality of input circuits being disposed on a side of the pixel peripheral circuit region furthest from the light-incident side of the first substrate. ### Claim 13 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the second substrate includes a signal processing circuit region. ### Claim 14 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the first substrate and the second substrate are electrically connected to one another with a twin contact structure. ### Claim 15 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the first substrate and the second substrate are electrically connected to one another with a shared contact structure. ### Claim 16 (depends on 2) The solid-state imaging apparatus according to claim 2, wherein the first substrate and the second substrate are electrically connected to one another through Cu—Cu bonding. ### Claim 17 (depends on 2) The solid-state imaging apparatus according to claim 2, further comprising: an on-chip lens on the pixel array unit; and a protective substrate on the on-chip lens. ### Claim 18 (depends on 2) The solid-state imaging apparatus according to claim 2, further comprising: a third substrate including a data holding unit. ### Claim 19 A manufacturing method of a solid-state imaging apparatus, the manufacturing method comprising: bonding a first structure to a second structure, the first structure including a pixel array unit in which pixels that perform photoelectric conversion are two-dimensionally arranged, the second structure including an output circuit to output pixel signals from the pixels to an external device, the output circuit being on a side of the pixel array unit furthest from a light-incident side so that wiring layers of the output circuit and the pixel array unit face each other; forming a through hole that penetrates through a semiconductor substrate of the second structure; and forming a terminal that is electrically connected to the output circuit via the through hole, the terminal being connectable to the external device at a position at a side of the pixel array unit furthest from the light-incident side of the first structure. ### Claim 20 An electronic device comprising: a solid-state imaging apparatus including: a first substrate including a pixel layer and a first wiring layer electrically connected to one another, the pixel layer including a pixel array unit with pixels for performing photoelectric conversion, the pixels being two-dimensionally arranged in the pixel layer, wherein the first substrate includes a first bonding layer, and wherein the first bonding layer includes one or more of an oxide, a nitride material, or carbon; and a second substrate including: a second wiring layer including at least one output circuit to output pixel signals from the pixels; and a second bonding layer, wherein the second bonding layer includes one or more of an oxide, a nitride material, or carbon; a connection layer including a first through hole that penetrates through the connection layer to the at least one output circuit; and a first terminal to electrically connect the at least one output circuit to an external device via the first through hole, wherein the first wiring layer and the second wiring layer are between the pixel layer and the connection layer, and wherein the first substrate is directly bonded to the second substrate via the first bonding layer and the second bonding layer.