# US 10,320,602 B2 · Data processing method and data processing apparatus

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- Number: US 10,320,602 B2
- Document ID: US10320602B2
- Status: Granted
- Kind: B2
- Application number: 15/644,350
- Filed: 2017-07-07
- Published: 2017-10-26
- Granted: 2019-06-11
- Earliest claimed: 2015-01-08
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Wenbin Yang; Xinyuan Wang; Tongtong Wang
- Web page: https://patentgrep.com/patent/US10320602B2

## CPC

- H04L 27/38: Demodulator circuits; Receiver circuits
- H04B 14/023: {using pulse amplitude modulation}
- H04L 1/0045: {Arrangements at the receiver end}
- H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)}
- H04L 25/4917: {using multilevel codes}
- H04L 25/493: by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04B: TRANSMISSION

## Abstract

A data processing method and an apparatus, where the method includes receiving m data streams using m receive ports respectively, where the m data streams include m×m data units, and the m×m data units form an m-order matrix A, keeping a location of one element in each row in the matrix A unchanged and moving remaining m−1 elements to remaining m−1 rows respectively in order to form an m-order matrix B, where a column number of each element in the remaining m−1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix B after the element is moved, and sending using m transmit ports, the m×m elements in the matrix B to m different levels of a pulse amplitude modulation (PAM) circuit respectively for performing modulation.

## Claims

### Claim 1

A data processing method, comprising:
receiving, by an encoding circuit, m data streams using m receive ports respectively, wherein m is an integer greater than 1, wherein the m receive ports are in a one-to-one correspondence with the m data streams, wherein the m data streams comprise m×m data units, wherein each data stream of the m data streams comprises m data units, wherein the m×m data units form an m-order matrix A, wherein the m×m data units are m×m elements in the matrix A, wherein m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received by the encoding circuit at a same time, and wherein among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received earlier than an element located on a left side;
keeping, by the encoding circuit, a location of one element in each row in the matrix A unchanged and moving remaining m−1 elements to remaining m−1 rows respectively to form an m−order matrix B, wherein a column number of each element in the remaining m−elements in the matrix A before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix B after the element is moved, and wherein the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B; and
sending, by the encoding circuit using m transmit ports, the m×m elements in the matrix B to m different levels of a pulse amplitude modulation (PAM) circuit respectively to perform modulation, wherein m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent at a same time, wherein among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent earlier than an element located on a left side, wherein the m×m elements in the matrix A are denoted by aij, wherein the m×m elements in the matrix B are denoted by bij, wherein i=1, . . ., m, wherein j=1, . . ., m, wherein bij=axj, and wherein a value of x is:
x=i+k when i+k≤m;
x=i+k−m when i+k>m;
x=i−k when i−k>0; and
x=i−k+m when i−k≤0,
wherein k is an integer greater than or equal to 0 and less than m, and
wherein m elements in a same row in the matrix B correspond to different k values respectively.

### Claim 2 (depends on 1)

The data processing method of claim 1, wherein a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

### Claim 3 (depends on 1)

The data processing method of claim 1, further comprising:
receiving, by the encoding circuit, the m data units using the m receive ports respectively, wherein the received m data units are in a one-to-one correspondence with the m receive ports, wherein the received m data units are received at a same time, and wherein a time at which the encoding circuit receives the received m data units is different from a time at which the encoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A; and
sending, by the encoding circuit using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively to perform modulation, wherein the received m data units are in a one-to-one correspondence with the m different levels of the PAM circuit.

### Claim 4

A data processing method, comprising:
receiving, by a decoding circuit, m demodulated data streams using m receive ports respectively, wherein m is an integer greater than 1, wherein the m receive ports are in a one-to-one correspondence with the m demodulated data streams, wherein the m demodulated data streams comprise m×m data units, wherein each data stream of the m demodulated data streams comprises m data units, wherein the m×m data units form an m−order matrix C, wherein the m×m data units are m×m elements in the matrix C, wherein m 1×m matrices in the matrix C are in a one-to-one correspondence with the m demodulated data streams, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received at a same time, and wherein among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received earlier than an element located on a left side;
keeping, by the decoding circuit, a location of one element in each row in the matrix C unchanged and moving remaining m−1 elements to remaining m−1 rows respectively in order to form an m−order matrix D, wherein a column number of each element in the remaining m−1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix D after the element is moved, and wherein the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D; and
sending, by the decoding circuit, the m×m elements in the matrix D using m transmit ports, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are sent at a same time, wherein among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent by the decoding circuit earlier than an element located on a left side, wherein the m×m elements in the matrix C are denoted by cij, wherein the m×m elements in the matrix D are denoted by dij, wherein i=1, . . ., m, wherein j=1, . . ., m, wherein dij=cyj, and wherein a value of y is:
y=i−k when i−k>0;
y=i−k+m when i−k≤0;
y=i+k when i+k≤m; and
y=i+k−m when i+k>m,
wherein k is an integer greater than or equal to 0 and less than m, and
wherein m elements in a same row in the matrix D correspond to different k values respectively.

### Claim 5 (depends on 4)

The data processing method of claim 4, wherein a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

### Claim 6 (depends on 4)

The data processing method of claim 4, further comprising:
receiving, by the decoding circuit, m demodulated data units using the m receive ports respectively, wherein the received m demodulated data units are in a one-to-one correspondence with the m receive ports, wherein the received m demodulated data units are received at a same time, and wherein a time at which the decoding circuit receives the received m demodulated data units is different from a time at which the decoding circuit receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C; and
sending, by the decoding circuit, the received m demodulated data units using the m transmit ports respectively, wherein the received m demodulated data units are in a one-to-one correspondence with the m transmit ports.

### Claim 7

A data processing apparatus, comprising:
a receiver configured to receive m data streams using m receive ports respectively, wherein m is an integer greater than 1, wherein the m receive ports are in a one-to-one correspondence with the m data streams, wherein the m data streams comprise m×m data units, wherein each data stream of the m data streams comprises m data units, wherein the m×m data units form an m-order matrix A, wherein the m×m data units are m×m elements in the matrix A, wherein m 1×m matrices in the matrix A are in a one-to-one correspondence with the m data streams, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix A are received at a same time, and wherein among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix A, an element located on a right side is received earlier than an element located on a left side;
a processor coupled to the receiver and configured to keep a location of one element in each row in the matrix A received by the receiver unchanged and move remaining m−1 elements to remaining m−1 rows respectively in order to form an m−order matrix B, wherein a column number of each element in the remaining m−1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix B after the element is moved, and wherein the m×m elements in the matrix A are in a one-to-one correspondence with m×m elements in the matrix B; and
a transmitter coupled to the receiver and the processor and configured to send, using m transmit ports, the m×m elements in the matrix B generated by the processor to m different levels of a pulse amplitude modulation (PAM) circuit respectively to perform modulation, wherein m 1×m matrices in the matrix B are in a one-to-one correspondence with the m different levels of the PAM circuit, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix B are sent at a same time, wherein among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix B, an element located on a right side is sent earlier than an element located on a left side, wherein the m×m elements in the matrix A are denoted by aij, wherein the m×m elements in the matrix B are denoted by bij, wherein i=1, . . ., m, wherein j=1, . . ., m, wherein bij=axj, and wherein a value of x is:
x=i+k when i+k≤m;
x=i+k−m when i+k>m;
x=i−k when i−k>0; and
x=i−k+m when i−k≤0,
wherein k is an integer greater than or equal to 0 and less than m, and
wherein m elements in a same row in the matrix B correspond to different k values respectively.

### Claim 8 (depends on 7)

The data processing apparatus of claim 7, wherein a difference between k values corresponding to two adjacent elements of elements in each row in the matrix B is 1.

### Claim 9 (depends on 7)

The data processing apparatus of claim 7, wherein the receiver is further configured to receive the m data units using the m receive ports respectively, wherein the received m data units are in a one-to-one correspondence with the m receive ports, wherein the received m data units are received at a same time, wherein a time at which the receiver receives the received m data units is different from a time at which the receiver receives m data units in any m×1 matrix of the m m×1 matrices in the matrix A, wherein the transmitter is further configured to send, using the m transmit ports, the received m data units to the m different levels of the PAM circuit respectively to perform modulation, and wherein the received m data units are in a one-to-one correspondence with the m different levels of the PAM circuit.

### Claim 10

A data processing apparatus, comprising:
a receiver configured to receive m demodulated data streams using m receive ports respectively, wherein m is an integer greater than 1, wherein the m receive ports are in a one-to-one correspondence with the m demodulated data streams, wherein the m demodulated data streams comprise m×m data units, wherein each data stream of the m demodulated data streams comprises m data units, wherein the m×m data units form an m−order matrix C, wherein the m×m data units are m×m elements in the matrix C, wherein m 1×m matrices in the matrix C are in a one-to-one correspondence with the m demodulated data streams, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix C are received at a same time, and wherein among m elements located in a same 1×m matrix of the m 1×m matrices in the matrix C, an element located on a right side is received earlier than an element located on a left side;
a processor coupled to the receiver and configured to keep a location of one element in each row in the matrix C received by the receiver unchanged and move remaining m−1 elements to remaining m−1 rows respectively in order to form an m−order matrix D, wherein a column number of each element in the remaining m−1 elements in the matrix C before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix D after the element is moved, and wherein the m×m elements in the matrix C are in a one-to-one correspondence with m×m elements in the matrix D; and
a transmitter coupled to the receiver and the processor and configured to send, using m transmit ports, the m×m elements in the matrix D generated by the processor, wherein m elements located in a same m×1 matrix of m m×1 matrices in the matrix D are from the transmitter at a same time, wherein among m elements located in a same 1×m matrix of m 1×m matrices in the matrix D, an element located on a right side is sent earlier than an element located on a left side, wherein the m×m elements in the matrix C are denoted by cij, wherein the m×m elements in the matrix D are denoted by dij, wherein i=1, . . ., m, wherein j=1, . . ., m, wherein dij =cyj, and wherein a value of y is:
y=i−k when i−k>0;
y=i−k+m when i−k≤0;
y=i+k when i+k≤m; and
y=i+k−m when i+k>m,
wherein k is an integer greater than or equal to 0 and less than m, and
wherein m elements in a same row in the matrix D correspond to different k values respectively.

### Claim 11 (depends on 10)

The data processing apparatus of claim 10, wherein a difference between k values corresponding to two adjacent elements of elements in each row in the matrix D is 1.

### Claim 12 (depends on 10)

The data processing apparatus of claim 10, wherein the receiver is further configured to receive m demodulated data units using the m receive ports respectively, wherein the received m demodulated data units are in a one-to-one correspondence with the m receive ports, wherein the received m demodulated data units are received at a same time, wherein a time at which the receiver receives the received m demodulated data units is different from a time at which the receiver receives m data units in any m×1 matrix of the m m×1 matrices in the matrix C, wherein the transmitter is further configured to send the received m demodulated data units using the m transmit ports respectively, and wherein the received m demodulated data units are in a one-to-one correspondence with the m transmit ports.