# US 10,320,595 B2 · Optimized CORDIC for APSK applications

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,320,595 B2
- Document ID: US10320595B2
- Status: Granted
- Kind: B2
- Application number: 16/010,490
- Filed: 2018-06-17
- Published: 2018-12-27
- Granted: 2019-06-11
- Earliest claimed: 2017-06-23
- Assignees: Instituto de Pesquisas Eldorado
- Applicants: Instituto de Pesquisas Eldorado
- Inventors: Eduardo Rodrigues de Lima; Tiago Diadami Perez
- Web page: https://patentgrep.com/patent/US10320595B2

## CPC

- H04L 27/06: Demodulator circuits; Receiver circuits
- G06F 7/5446: {using crossaddition algorithms, e.g. CORDIC}
- H04B 1/16: Circuits
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04B: TRANSMISSION

## Abstract

A reduced COordinate Rotation DIgital Computer (CORDIC) cell in a parallel CORDIC has an xy-path from x and y inputs to x and y outputs, and a z-path from a z-input to a z-output. Bit-shifts in the xy-path are hardwired. The z-path has a shortened adder/subtractor with a built-in or hardwired fixed parameter. Input bits from the z-input are split into most significant and least significant bits. The number of most significant bits equals the shortened adder/subtractor width. The most significant bits are input to the non-inverting inputs of the adder/subtractor for calculating the most significant z-output bits. The least significant bits are connected directly (or via buffers) from the z-input to the z-output.

## Claims

### Claim 1

A COordinate Rotation DIgital Computer (CORDIC) with a first bit-width, the CORDIC comprising:
multiple stages of three-dimensional CORDIC cells capable of performing vector rotation, wherein at least one of the CORDIC cells comprises a reduced CORDIC cell with an xy-path and a z-path wherein:
bit-shifts in the xy-path are hardwired;
a z-path fixed parameter is truncated to a second bit-width that is smaller than the first bit-width;
a z-path adder/subtractor is shortened to the second bit-width;
the truncated fixed parameter is included in the shortened adder/subtractor;
a number of most significant bits of a reduced CORDIC cell z-input word is coupled to non-inverting inputs of the shortened adder/subtractor, wherein the number of most significant bits equals the second bit-width;
the shortened adder/subtractor provides a number of most significant bits of a reduced CORDIC cell output word, wherein the number of most significant bits equals the second bit-width; and
a number of least significant bits of the reduced CORDIC cell output word is coupled with a number of least significant bits of the reduced CORDIC cell input word, wherein the number of least significant bits equals the first bit-width minus the second bit-width.

### Claim 2 (depends on 1)

The CORDIC of claim 1, wherein:
the truncated fixed parameter is included in the shortened adder/subtractor by coupling bits of invertible inputs of the shortened adder/subtractor to respective logic levels representing the truncated fixed parameter.

### Claim 3 (depends on 1)

The CORDIC of claim 1, wherein:
the truncated fixed parameter is rounded before truncation.

### Claim 4 (depends on 3)

The CORDIC of claim 3, wherein:
the truncated fixed parameter is rounded from a value arctan(2−i) to a value 2−i.

### Claim 5 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor is capable of adding only, and the truncated fixed parameter is included in the shortened adder/subtractor by coupling bits of non-inverting inputs of the shortened adder/subtractor to respective bit levels provided by a sign bit value and by an inverted value of the sign bit.

### Claim 6 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor includes a ripple-carry adder.

### Claim 7 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor includes a carry-lookahead adder.

### Claim 8 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor includes a carry-save adder.

### Claim 9 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor has been logically optimized, while preserving its truth table, to include fewer gates.

### Claim 10 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor has been logically optimized, while preserving its truth table, to decrease latency.

### Claim 11 (depends on 1)

The CORDIC of claim 1, wherein:
the shortened adder/subtractor has been logically optimized, while preserving its truth table, to decrease power.

### Claim 12 (depends on 1)

The CORDIC of claim 1, wherein:
a least significant bit of the reduced CORDIC cell output word is coupled with a least significant bit of the reduced CORDIC cell input word via a buffer cell.

### Claim 13 (depends on 1)

The CORDIC of claim 1, wherein:
two or more of the multiple stages of three-dimensional CORDIC cells are separated by pipeline registers to increase a CORDIC throughput rate.

### Claim 14 (depends on 1)

The CORDIC of claim 1, wherein:
at least one of the CORDIC cells comprises a full CORDIC cell with an xy-path and a z-path wherein:
bit-shifts in the xy-path are hardwired; and
a z-path fixed parameter is included in the shortened adder/subtractor.

### Claim 15

A method to perform a vector micro-rotation in a CORDIC cell, comprising:
directly forwarding bits of x-input and y-input signals to a first adder/subtractor and a second adder/subtractor to calculate x-output and y-output bits, respectively, wherein the directly forwarding may comprise forwarding the bits of the x-input and y-input signals via buffers but not via multiplexers;
forwarding a first part of bits from a z-input signal to a shortened adder/subtractor, and a second part of the bits from the z-input signal to a second part of bits from a z-output signal, wherein the forwarding the second part of the bits is directly, and wherein the forwarding directly may comprise forwarding the second part of the bits via buffers; and
in the shortened adder/subtractor, one of adding bits of a truncated rounded fixed parameter to and subtracting bits of the truncated rounded fixed parameter from the first part of the bits from the z-input signal, to calculate a first part of the bits from the z-output signal.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the shortened adder/subtractor includes a ripple-carry adder.

### Claim 17 (depends on 15)

The method of claim 15, wherein:
the first adder/subtractor includes a carry-lookahead adder.

### Claim 18 (depends on 15)

The method of claim 15, wherein:
the first adder/subtractor includes a carry-save adder.

### Claim 19 (depends on 15)

The method of claim 15, wherein:
the shortened adder/subtractor has been logically optimized while preserving its truth table.

### Claim 20 (depends on 15)

The method of claim 15, wherein:
the first adder/subtractor has been logically optimized while preserving its truth table.