# US 10,320,534 B2 · Receiver clock test circuitry and related methods and apparatuses > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,534 B2 - Document ID: US10320534B2 - Status: Granted - Kind: B2 - Application number: 15/872,885 - Filed: 2018-01-16 - Published: 2018-08-30 - Granted: 2019-06-11 - Earliest claimed: 2012-05-02 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Srinivasaraman Chandrasekaran; Kunal Desai - Web page: https://patentgrep.com/patent/US10320534B2 ## CPC - H04L 1/205: {jitter monitoring} - G01R 31/31709: {Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901)} - G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals} - H04L 1/241: {using pseudo-errors} - H04L 1/242: {by comparing a transmitted test signal with a locally generated replica} - H04L 7/0079: {Receiver details} - H04L 7/0083: {taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks} - H04L 7/10: Arrangements for initial synchronisation - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. ## Claims ### Claim 1 An integrated circuit to receive an incoming data signal from a transmitter, the incoming data signal arriving via a conductive path, the integrated circuit comprising: a register to storage at least one programmable parameter; a receiver to sample the incoming data signal at sampling times established relative to a reference clock, to responsively generate a sequence of data samples when the receiver is operated in a first mode and when the receiver is operated in a second mode; circuitry to inject a pattern of variation into the reference clock when the receiver is operated in the first mode, the pattern of variation dependent on the at least one programmable parameter, such that the sampling times during the first mode are distorted when the receiver is operated in the first mode, according to the pattern of variation; and circuitry to detect mismatch between an expected symbol pattern and samples from the sequence of data samples obtained while the receiver is operated in the first mode. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein: the at least one programmable parameter comprises a value established so as cause the circuitry to inject to inject at least one of a random, sinusoidal or spread spectrum jitter pattern into the reference clock. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein: the first mode is a test mode; and the integrated circuit comprises a pseudorandom bit generator to generate the expected symbol pattern, and a circuit to synchronize an output of the pseudorandom bit generator with a test pattern to be transmitted by the transmitter as part of the incoming data signal during the test mode. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein: the at least one programmable parameter comprises a value established so as cause the circuitry to inject at least one of a pattern of phase offsets or a pattern of frequency offsets into the reference clock. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein: the integrated circuit further comprises a clock recovery circuit to generate a recovered clock; and the reference clock is based on the recovered clock during the first mode. ### Claim 6 (depends on 5) The integrated circuit of claim 5, wherein: the integrated circuit further comprises a clock selection circuit; and the clock selection circuit is controlled such that the reference clock is selected to be a first clock when the receiver is operated in the second mode and such that the reference clock is selected to be the recovered clock when the receiver is operated in the first mode. ### Claim 7 (depends on 5) The integrated circuit of claim 5, wherein: the receiver is a first receiver and the incoming data signal is a first incoming data signal; the integrated circuit further comprises a second receiver to receive a second incoming data signal arriving via a second conductive path; and the clock recovery circuit is to generate the recovered clock dependent on symbol transitions in the second incoming data signal. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein: when the first receiver is operated in the second mode, the second receiver is to sample the second incoming data signal at second sampling times which are dependent on the recovered clock. ### Claim 9 (depends on 5) The integrated circuit of claim 5, wherein: the clock recovery circuit comprises at least one of a phase accumulator and a frequency accumulator; and the circuitry to inject the pattern of variation is to inject a sequence of predetermined offsets into the at least one of the phase accumulator and the frequency accumulator of the clock recovery circuit when the receiver is operated in the first mode. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein: the pattern of variation is a nonlinear pattern, such that the sampling times during the first mode are distorted in a nonlinear manner when the receiver is operated in the first mode, according to the nonlinear pattern of variation. ### Claim 11 An integrated circuit to receive an incoming data signal from a transmitter, the incoming data signal arriving via a conductive path, the integrated circuit comprising: a register to storage at least one programmable parameter; a receiver to sample the incoming data signal at sampling times established relative to a reference clock, to responsively generate a sequence of data samples when the receiver is operated in a test mode and when the receiver is operated in a normal mode; circuitry to inject a pattern of variation into the reference clock when the receiver is operated in the test mode, the pattern of variation dependent on the at least one programmable parameter, such that the sampling times during the first mode are distorted when the receiver is operated in the test mode, according to the pattern of variation; and circuitry to detect mismatch between an expected symbol pattern and samples from the sequence of data samples obtained while the receiver is operated in the test mode; wherein the at least one programmable parameter comprises a value established so as cause the circuitry to inject to inject at least one of a random, sinusoidal or spread spectrum jitter pattern into the reference clock. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein: the integrated circuit comprises a pseudorandom bit generator to generate the expected symbol pattern, and a circuit to synchronize an output of the pseudorandom bit generator with a test pattern to be transmitted by the transmitter as part of the incoming data signal during the test mode. ### Claim 13 (depends on 11) The integrated circuit of claim 11, wherein: the at least one programmable parameter comprises a value established so as cause the circuitry to inject at least one of a pattern of phase offsets or a pattern of frequency offsets into the reference clock. ### Claim 14 (depends on 11) The integrated circuit of claim 11, wherein: the integrated circuit further comprises a clock recovery circuit to generate a recovered clock; and the reference clock is based on the recovered clock during the test mode. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein: the integrated circuit further comprises a clock selection circuit; and the clock selection circuit is controlled such that the reference clock is selected to be a first clock when the receiver is operated in the normal mode and such that the reference clock is selected to be the recovered clock when the receiver is operated in the test mode. ### Claim 16 (depends on 14) The integrated circuit of claim 14, wherein: the receiver is a first receiver and the incoming data signal is a first incoming data signal; the integrated circuit further comprises a second receiver to receive a second incoming data signal arriving via a second conductive path; and the clock recovery circuit is to generate the recovered clock dependent on symbol transitions in the second incoming data signal. ### Claim 17 (depends on 16) The integrated circuit of claim 16, wherein: when the first receiver is operated in the second mode, the second receiver is to sample the second incoming data signal at second sampling times which are dependent on the recovered clock. ### Claim 18 (depends on 14) The integrated circuit of claim 14, wherein: the clock recovery circuit comprises at least one of a phase accumulator and a frequency accumulator; and the circuitry to inject the pattern of variation is to inject a sequence of predetermined offsets into the at least one of the phase accumulator and the frequency accumulator of the clock recovery circuit when the receiver is operated in the first mode. ### Claim 19 An integrated circuit to receive an incoming data signal from a transmitter, the incoming data signal arriving via a conductive path, the integrated circuit comprising: a register to storage at least one programmable parameter; a receiver to sample the incoming data signal at sampling times established relative to a reference clock, to responsively generate a sequence of data samples when the receiver is operated in a first mode and when the receiver is operated in a second mode; circuitry to inject a pattern of variation into the reference clock when the receiver is operated in the first mode, the pattern of variation dependent on the at least one programmable parameter, such that the sampling times during the first mode are distorted when the receiver is operated in the first mode, according to the pattern of variation; and circuitry to detect mismatch between an expected symbol pattern and samples from the sequence of data samples obtained while the receiver is operated in the first mode; wherein the first mode is a test mode, wherein integrated circuit further comprises a clock recovery circuit to generate a recovered clock, and wherein the reference clock is based on the recovered clock when the receiver is operated in the first mode. ### Claim 20 (depends on 19) The integrated circuit of claim 19, wherein: the receiver is a first receiver and the incoming data signal is a first incoming data signal; the integrated circuit further comprises a second receiver to receive a second incoming data signal arriving via a second conductive path, and a clock selection circuit; and the clock recovery circuit is to generate the recovered clock dependent on symbol transitions in the second incoming data signal; and the clock selection circuit is controlled such that the reference clock is selected to be a first clock when the receiver is operated in the second mode and such that the reference clock is selected to be the recovered clock when the receiver is operated in the first mode. ### Claim 21 (depends on 20) The integrated circuit of claim 20, wherein: when the first receiver is operated in the second mode, the second receiver is to sample the second incoming data signal at second sampling times which are dependent on the recovered clock. ### Claim 22 (depends on 19) The integrated circuit of claim 19, wherein: the pattern of variation is a nonlinear pattern, such that the sampling times during the first mode are distorted in a nonlinear manner when the receiver is operated in the first mode, according to the nonlinear pattern of variation.