# US 10,320,428 B2 · Outputting of codeword bits for transmission prior to loading all input bits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,428 B2 - Document ID: US10320428B2 - Status: Granted - Kind: B2 - Application number: 15/616,792 - Filed: 2017-06-07 - Published: 2018-02-15 - Granted: 2019-06-11 - Earliest claimed: 2016-08-15 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Gabi Sarkis; Yang Yang; Jing Jiang; Jamie Menjay Lin; John Edward Smee - Web page: https://patentgrep.com/patent/US10320428B2 ## CPC - H03M 13/3761: {using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes} - H03M 13/13: Linear codes - H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding} - H03M 13/6525: {3GPP LTE including E-UTRA} - H04L 1/00: Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} - H04L 1/0041: {Arrangements at the transmitter end} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 1/0058: {Block-coded modulation} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Methods, systems, and devices for outputting of codeword bits for transmission prior to loading all input bits. An example encoder may have multiple encoding branches. The encoder may divide the encoding branches into first and second encoding branch subsets, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. The encoder may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. The encoder may output the first subset of output bits prior to outputting the second subset of output bits. ## Claims ### Claim 1 A method for encoding by an encoder comprising a plurality of encoding branches, the method comprising: dividing the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset; generating first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset; outputting, from the encoder, the first subset of output bits prior to outputting the second subset of output bits; and transmitting, via a wireless communication channel, the first subset of output bits prior to transmitting, via a wireless communication channel, the second subset of output bits. ### Claim 2 (depends on 1) The method of claim 1, further comprising: receiving, at the encoder, a first of a plurality of subsets of the information bits of the information bit-vector prior to receiving a last of the plurality of subsets of the information bits from the information bit-vector. ### Claim 3 (depends on 2) The method of claim 2, wherein the outputting of the first subset of output bits is performed prior to the receiving of the last of the plurality of subsets of the information bits of the information bit-vector. ### Claim 4 (depends on 1) The method of claim 1, further comprising: receiving, by the encoder, the information bits of the information bit-vector for generating the codeword at a constant rate. ### Claim 5 (depends on 1) The method of claim 1, further comprising: receiving, by the encoder, the information bits of the information bit-vector for generating the codeword at a variable rate. ### Claim 6 (depends on 1) The method of claim 1, further comprising: determining a code rate for the encoding by selecting a number of frozen bits for input to the plurality of encoding branches. ### Claim 7 (depends on 1) The method of claim 1, further comprising: performing bit-reversal on input indices of the plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to the dividing of the plurality of encoding branches. ### Claim 8 (depends on 7) The method of claim 7, wherein a first subset of the bit-reversed indices correspond to the first encoding branch subset and a second subset of the bit-reversed indices correspond to the second encoding branch subset, and wherein each bit-reversed index in the first subset of the bit-reversed indices has a higher number than each bit-reversed index in the second subset of the bit-reversed indices. ### Claim 9 (depends on 8) The method of claim 8, wherein the first subset of output bits correspond to a first subset of the output indices of the plurality of encoding branches and the second subset of output bits correspond to a second subset of the output indices of the plurality of encoding branches, and wherein the first subset of the output indices and the second subset of the output indices are interleaved with each other. ### Claim 10 (depends on 8) The method of claim 8, wherein the second subset of output bits is dependent on the first subset of output bits and bits input to the second encoding branch subset. ### Claim 11 (depends on 1) The method of claim 1, wherein the encoder is a linear block encoder. ### Claim 12 (depends on 1) The method of claim 1, wherein generating the first and second subsets of output bits of the codeword in first and second encoding operations comprises: inputting a first subset of the information bits of the information bit-vector and a first error detecting code generated from the first subset of the information bits to encoding branches of the first encoding branch subset for generating the first subset of output bits; and inputting a second subset of the information bits of the information bit-vector and a second error detecting code generated from the first subset of the information bits, the second subset of the information bits, or both the first and second subsets of the information bits, to encoding branches of the second encoding branch subset for generating the second subset of output bits. ### Claim 13 An apparatus for encoding, in a system comprising: a processor; memory in electronic communication with the processor; and instructions stored in the memory and operable, when executed by the processor, to cause the apparatus to: divide a plurality of encoding branches of an encoder into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset; generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset; output the first subset of output bits prior to outputting the second subset of output bits; and transmit, via a wireless communication channel, the first subset of output bits prior to transmitting, via a wireless communication channel, the second subset of output bits. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the instructions are further executable by the processor to: receive a first of a plurality of subsets of the information bits of the information bit-vector prior to receiving a last of the plurality of subsets of the information bits from the information bit-vector. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the outputting of the first subset of output bits is performed prior to the receiving of the last of the plurality of subsets of the information bits of the information bit-vector. ### Claim 16 (depends on 13) The apparatus of claim 13, wherein the instructions are further executable by the processor to: receive the information bits of the information bit-vector for generating the codeword at a constant rate. ### Claim 17 (depends on 13) The apparatus of claim 13, wherein the instructions are further executable by the processor to: receive the information bits of the information bit-vector for generating the codeword at a variable rate. ### Claim 18 (depends on 13) The apparatus of claim 13, wherein the instructions are further executable by the processor to: determine a code rate for the encoding by selecting a number of frozen bits for input to the plurality of encoding branches. ### Claim 19 (depends on 13) The apparatus of claim 13, wherein the instructions are further executable by the processor to: perform bit-reversal on input indices of the plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to the dividing of the plurality of encoding branches. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein a first subset of the bit-reversed indices correspond to the first encoding branch subset and a second subset of the bit-reversed indices correspond to the second encoding branch subset, and wherein each bit-reversed index in the first subset of the bit-reversed indices has a higher number than each bit-reversed index in the second subset of the bit-reversed indices. ### Claim 21 (depends on 20) The apparatus of claim 20, wherein the first subset of output bits correspond to a first subset of the output indices of the plurality of encoding branches and the second subset of output bits correspond to a second subset of the output indices of the plurality of encoding branches, and wherein the first subset of the output indices and the second subset of the output indices are interleaved with each other. ### Claim 22 (depends on 20) The apparatus of claim 20, wherein the second subset of output bits is dependent on the first subset of output bits and bits input to the second encoding branch subset. ### Claim 23 (depends on 13) The apparatus of claim 13, wherein the encoder is a linear block encoder. ### Claim 24 (depends on 13) The apparatus of claim 13, wherein generating the first and second subsets of output bits of the codeword in first and second encoding operations comprises instructions further executable by the processor to: input a first subset of the information bits of the information bit-vector and a first error detecting code generated from the first subset of the information bits to encoding branches of the first encoding branch subset for generating the first subset of output bits; and input a second subset of the information bits of the information bit-vector and a second error detecting code generated from the first subset of the information bits, the second subset of the information bits, or both the first and second subsets of the information bits, to encoding branches of the second encoding branch subset for generating the second subset of output bits. ### Claim 25 An apparatus for wireless communication, comprising: means for dividing a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset; means for generating first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset; means for outputting the first subset of output bits prior to outputting the second subset of output bits; and means for transmitting, via a wireless communication channel, the first subset of output bits prior to transmitting, via a wireless communication channel, the second subset of output bits. ### Claim 26 (depends on 25) The apparatus of claim 25, further comprising: means for performing bit-reversal on input indices of the plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to the dividing of the plurality of encoding branches. ### Claim 27 A non-transitory computer readable medium storing code for wireless communication, the code comprising instructions executable by a processor to: divide a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset; generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset; output the first subset of output bits prior to outputting the second subset of output bits; and transmit, via a wireless communication channel, the first subset of output bits prior to transmitting, via a wireless communication channel, the second subset of output bits. ### Claim 28 (depends on 27) The non-transitory computer-readable medium of claim 27, wherein the instructions are further executable by the processor to: perform bit-reversal on input indices of the plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to the dividing of the plurality of encoding branches.