# US 10,320,425 B2 · Staircase forward error correction coding

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- Number: US 10,320,425 B2
- Document ID: US10320425B2
- Status: Granted
- Kind: B2
- Application number: 15/194,432
- Filed: 2016-06-27
- Published: 2016-10-20
- Granted: 2019-06-11
- Earliest claimed: 2011-04-13
- Assignees: Inphi Corporation
- Applicants: Inphi Corporation
- Inventors: Arash Farhoodfar; Frank R. Kschischang; Andrew Hunt; Benjamin P. Smith; John Lodge
- Web page: https://patentgrep.com/patent/US10320425B2

## CPC

- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/15: Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence)
- H03M 13/2707: {Simple row-column interleaver, i.e. pure block interleaving}
- H03M 13/2721: {the interleaver involves a diagonal direction, e.g. by using an interleaving matrix with read-out in a diagonal direction}
- H03M 13/2918: {with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube}
- H03M 13/2927: {Decoding strategies}
- H03M 13/3746: {with iterative decoding}
- H03M 13/616: {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations}
- H04J 3/1658: {carrying packets or ATM cells; (H04J3/1664 takes precedence for payloads with different packet types)}
- H04J 14/08: Time-division multiplex systems
- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code. Thus, each row in [Bi−1T Bi] and each column in [ B i B i + 1 T ] , for example, is a valid codeword.

## Claims

### Claim 1

An apparatus comprising:
a mapper to receive a stream of data symbols from a transport network and to map the stream of data symbols among data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer, each of the symbol blocks comprising data symbol positions and coding symbol positions; and
a Forward Error Correction (FEC) encoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the mapper, to process coding symbols for the coding symbol positions in each symbol block in the sequence, the coding symbols being processed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with symbols at symbol positions along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code,
wherein each symbol block comprises an n row by m column array of symbols, m, n≥1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block Bi based on Di−1 and Bi, where Di−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of Bi−1.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the mapper maps the stream of data symbols to the symbol positions from one or more Optical channel Transport Unit (OTUk) frames.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the predetermined symbols comprise all zeros.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the symbol blocks comprise 512 rows by 510 columns of bits, and wherein the FEC component code comprises a Bose-Chaudhuri-Hocquenghem (1022, 990) code.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the mapping comprises mapping information bits of two Optical channel Transport Unit (OTUk) frames to information symbols in each symbol block Bi, i≥1, the method further comprising:
mapping the coding symbols in each symbol block Bi−1, i≥2, to parity bits of the two OTUk frames to which the information symbols in symbol block Bi are mapped.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the symbol blocks comprise 196 rows by 187 columns of bits, and wherein the FEC component code comprises a Bose-Chaudhuri-Hocquenghem (383, 353) code.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the mapping comprises mapping information bits of one of four rows of an Optical channel Transport Unit (OTUk) frame to information symbols in each symbol block Bi, i≥1, and
mapping the coding symbols in each symbol block Bi−1, i≥2, to parity bits of the Optical channel Transport Unit (OTUk) frame to which the information symbols in symbol block Bi are mapped.

### Claim 8

An apparatus that comprises:
an interface to receive a sequence of FEC encoded two-dimensional symbol blocks Bi, i a positive integer, each of the received symbol blocks comprising received versions of data symbols at data symbol positions and coding symbols at coding symbol positions, the coding symbols for the coding symbol positions in each symbol block Bi in the sequence having been processed at a transmitter of the received symbol blocks such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with symbols at symbol positions along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code; and
an FEC decoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the interface, to decode the received FEC encoded symbol blocks,
wherein each symbol block comprises an n row by m column array of symbols, m, n>1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block Bi based on Di−1 and Bi, where Di−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of Bi−1.