Loading patent…
AssigneeTeledyne E2V Semiconductors SAS
InventorsEtienne Bouin, Rémi Laube, Jérôme Ligozat, Marc Stackler
Estimating the term…
In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.
A method for synchronizing digital/analogue and/or analogue/digital data converters to an active front of a common reference clock CLK, characterized in that the converters form at least one series transmission chain allowing a synchronizing signal emitted by a unit for controlling the converters to be transmitted, method such that:
An analogue/digital or digital/analogue data converter comprising an input for receiving a synchronizing signal and an associated synchronizing circuit allowing the converter to be synchronized to an active front of a reference-clock signal, the converter comprising a configuration register that may be read from and written to via an interface bus by a control unit of the converter, said register comprising at least one polarity parameter defining a reference-clock-front polarity for detection of said synchronizing signal received as input, and the synchronizing circuit comprising a detecting circuit that comprises:
Dependencies are inferred from the claim text.