# US 10,320,401 B2 · Dual-path digital-to-time converter

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- Number: US 10,320,401 B2
- Document ID: US10320401B2
- Status: Granted
- Kind: B2
- Application number: 15/784,022
- Filed: 2017-10-13
- Published: 2019-04-18
- Granted: 2019-06-11
- Earliest claimed: 2017-10-13
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Augusto R. Ximenes; Bob W. Verbruggen; Christophe Erdmann
- Web page: https://patentgrep.com/patent/US10320401B2

## CPC

- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/0992: {comprising a counter or a frequency divider}
- H03L 7/0994: {comprising an accumulator}
- H03K 2005/00071: {by adding capacitance as a load}
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

## Claims

### Claim 1

A digital-to-time converter (DTC), comprising:
a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal, wherein each of the plurality of delay cells includes a first multiplexer and first and second delay circuits coupled to the first multiplexer; and
a dynamic element matching (DEM) controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

### Claim 2 (depends on 1)

The DTC of claim 1, further comprising:
a phase detector coupled to an output of the delay chain circuit;
an accumulator coupled to an output of the phase detector; and
a calibration circuit coupled to an output of the accumulator and an input of the DEM controller, the calibration circuit including an input to receive a control signal.

### Claim 3 (depends on 1)

The DTC of claim 1, wherein each of the plurality of delay cells includes a first delay circuit and a second delay circuit, wherein the delay chain circuit includes a first path through the plurality of delay cells and a second path through the plurality of delay cells, and wherein each of the plurality of delay cells couples the first delay circuit thereof to the first path and the second delay circuit thereof to the second path, or the second delay circuit thereof to the first path and the first delay circuit thereof to the second path, based on a respective one of the plurality of control signals.

### Claim 4 (depends on 1)

The DTC of claim 1, wherein each of the plurality of delay cells includes a second multiplexer and first and second delay circuits coupled between the first and second multiplexers.

### Claim 5 (depends on 4)

The DTC of claim 4, wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of transmission gates.

### Claim 6 (depends on 4)

The DTC of claim 4, wherein the first and second delay circuits of each of the plurality of delay cells each include a first inverter, a second inverter, and a switched capacitor array coupled between the first and second inverters.

### Claim 7 (depends on 4)

The DTC of claim 4, wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of three-state inverters, and wherein the first and second delay circuits of each of the plurality of delay cells each include a switched capacitor array coupled between the first and second multiplexers.

### Claim 8 (depends on 1)

The DTC of claim 1, wherein the delay chain circuit includes a plurality of separate delay chains, each of the plurality of separate delay chains include a portion of the plurality of delay cells, and wherein the DEM controller includes a plurality of separate DEM controllers respectively coupled to the plurality of separate delay chains.

### Claim 9

A digital phase-locked loop (DPLL), comprising:
a digitally controlled oscillator (DCO) configured to generate a clock signal; and
a digital-to-time converter (DTC) having first input coupled to an output of the DCO and a second input configured to receive a reference clock signal, the DTC including:
a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive the reference clock signal and a second input to receive the clock signal, wherein each of the plurality of delay cells includes a first multiplexer and first and second delay circuits coupled to the first multiplexer; and
a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

### Claim 10 (depends on 9)

The DPLL of claim 9, wherein the DTC further comprises:
a phase detector coupled to an output of the delay chain circuit;
an accumulator coupled to an output of the phase detector; and
a calibration circuit coupled to an output of the accumulator and an input of the DEM controller, the calibration circuit including an input to receive a control signal.

### Claim 11 (depends on 9)

The DPLL of claim 9, wherein each of the plurality of delay cells includes a first delay circuit and a second delay circuit, wherein the delay chain circuit includes a first path through the plurality of delay cells and a second path through the plurality of delay cells, and wherein each of the plurality of delay cells couples the first delay circuit thereof to the first path and the second delay circuit thereof to the second path, or the second delay circuit thereof to the first path and the first delay circuit thereof to the second path, based on a respective one of the plurality of control signals.

### Claim 12 (depends on 9)

The DPLL of claim 9, wherein each of the plurality of delay cells includes a second multiplexer and first and second delay circuits coupled between the first and second multiplexers.

### Claim 13 (depends on 12)

The DPLL of claim 12, wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of transmission gates.

### Claim 14 (depends on 13)

The DPLL of claim 13, wherein the first and second delay circuits of each of the plurality of delay cells each include a first inverter, a second inverter, and a switched capacitor array coupled between the first and second inverters.

### Claim 15 (depends on 12)

The DPLL of claim 12, wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of three-state inverters, and wherein the first and second delay circuits of each of the plurality of delay cells each include a switched capacitor array coupled between the first and second multiplexers.

### Claim 16 (depends on 9)

The DPLL of claim 9, wherein the delay chain circuit includes a plurality of separate delay chains, each of the plurality of separate delay chains include a portion of the plurality of delay cells, and wherein the DEM controller includes a plurality of separate DEM controllers respectively coupled to the plurality of separate delay chains.

### Claim 17

A method of digital-to-time conversion, comprising:
coupling a first clock signal to a first delay path and a second clock signal to a second delay path, each of the first and second delay paths implemented by a delay chain circuit having a plurality of delay cells coupled in sequence, wherein each of the plurality of delay cells includes a multiplexer and first and second delay circuits coupled to the multiplexer;
providing a plurality of control signals to the plurality of delay cells to adjust delay of the first delay path with respect to the second delay path.

### Claim 18 (depends on 17)

The method of claim 17, wherein each of the plurality of delay cells includes a first delay circuit and a second delay circuit, and wherein each of the plurality of delay cells couples the first delay circuit thereof to the first delay path and the second delay circuit thereof to the second delay path, or the second delay circuit thereof to the first delay path and the first delay circuit thereof to the second delay path, based on a respective one of the plurality of control signals.