# US 10,320,394 B1 · Superconducting circuits for an A-and-not-B gate having an exclusive-OR gate and an AND gate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,394 B1 - Document ID: US10320394B1 - Status: Granted - Kind: B1 - Application number: 16/137,731 - Filed: 2018-09-21 - Granted: 2019-06-11 - Earliest claimed: 2018-09-21 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Jack R. Powell; Alexander L. Braun - Web page: https://patentgrep.com/patent/US10320394B1 ## CPC - H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical - H03K 19/0008: {Arrangements for reducing power consumption} - H03K 19/1952: {with electro-magnetic coupling of the control current} - H03K 19/1954: {with injection of the control current} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Superconducting circuits-based devices and methods for an A-and-not-B gate are provided. In one example, a circuit for an A-and-not-B gate including an output terminal, a first input terminal for receiving a first set of single flux quantum (SFQ) pulses, and a second input terminal for receiving a second set of SFQ pulses is provided. The circuit may further include a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result. The circuit may further include a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal and provide an output via the output terminal. ## Claims ### Claim 1 A circuit for an A-and-not-B gate comprising: an output terminal; a first input terminal for receiving a first set of single flux quantum (SFQ) pulses; a second input terminal for receiving a second set of SFQ pulses; a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result; and a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal and provide an output via the output terminal. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first stage comprises an escape junction. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the escape junction comprises a Josephson junction. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the first stage comprises a first inductor coupled between the first input terminal and a first node, a first Josephson junction coupled between the first node and a ground terminal, and a second inductor coupled between the first node and a second node. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the first stage further comprises a third inductor coupled between the second input terminal and a third node, a second Josephson junction coupled between the third node and the ground terminal, and an escape junction coupled between the second node and a fourth node. ### Claim 6 (depends on 5) The circuit of claim 5, wherein the second stage comprises a powered junction coupled between the fourth node and the output terminal. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the powered junction comprises a bias terminal coupled to an inductor for powering a third Josephson junction coupled between the fourth node and the ground terminal. ### Claim 8 A method of operating a circuit for an A-and-not-B gate, wherein the circuit including an output terminal, the method comprising: receiving a first set of single flux quantum (SFQ) pulses via a first input terminal; receiving a second set of SFQ pulses via a second input terminal; performing an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result; and performing an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal such that the circuit is configured to pass the first set of SFQ pulses to the output terminal only when inputs to the exclusive-OR operation differ and inputs to the AND operation are the same. ### Claim 9 (depends on 8) The method of claim 8, wherein the exclusive-OR operation is performed using a first stage and the AND operation is performed using a second stage coupled to the first stage. ### Claim 10 (depends on 9) The method of claim 9, wherein the first stage comprises an escape junction. ### Claim 11 (depends on 10) The method of claim 10, wherein the escape junction comprises a Josephson junction. ### Claim 12 (depends on 9) The method of claim 9, wherein the first stage comprises a first inductor coupled between the first input terminal and a first node, a first Josephson junction coupled between the first node and a ground terminal, and a second inductor coupled between the first node and a second node. ### Claim 13 (depends on 12) The method of claim 12, wherein in the first stage further comprises a third inductor coupled between the second input terminal and a third node, a second Josephson junction coupled between the third node and the ground terminal, and an escape junction coupled between the second node and a fourth node. ### Claim 14 (depends on 13) The method of claim 13, wherein the second stage comprises a powered junction coupled between the fourth node and the output terminal. ### Claim 15 (depends on 14) The method of claim 14, wherein the powered junction comprises a bias terminal coupled to an inductor for powering a third Josephson junction coupled between the fourth node and the ground terminal. ### Claim 16 A circuit for an A-and-not-B gate comprising: an output terminal; a first input terminal for receiving a first set of single flux quantum (SFQ) pulses; a powered junction coupled to the first input terminal; a second input terminal for receiving a second set of SFQ pulses; a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result; a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal such that the circuit is configured to pass the first set of SFQ pulses to the output terminal only when inputs to the exclusive-OR operation differ and inputs to the AND operation are the same; and a powered junction coupled to the output terminal. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the first stage comprises an escape junction. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the escape junction comprises a Josephson junction. ### Claim 19 (depends on 16) The circuit of claim 16, wherein the first stage comprises a first inductor coupled between the first input terminal and a first node, a first Josephson junction coupled between the first node and a ground terminal, and a second inductor coupled between the first node and a second node. ### Claim 20 (depends on 19) The circuit of claim 19, wherein in the first stage further comprises a third inductor coupled between the second input terminal and a third node, a second Josephson junction coupled between the third node and the ground terminal, and an escape junction coupled between the second node and a fourth node.