# US 10,320,391 B2 · Pulse-width modulation (PWM) control loop for power application > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,391 B2 - Document ID: US10320391B2 - Status: Granted - Kind: B2 - Application number: 16/154,938 - Filed: 2018-10-09 - Published: 2019-02-14 - Granted: 2019-06-11 - Earliest claimed: 2016-08-09 - Assignees: AnDAPT, Inc. - Applicants: AnDAPT, Inc. - Inventors: Kapil Shankar; Herman Cheung; John Birkner; Patrick J. Crotty - Web page: https://patentgrep.com/patent/US10320391B2 ## CPC - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H02M 3/157: with digital control - H03K 7/08: Duration or width modulation {; Duty cycle modulation} - H03K 19/17744: {for input/output signals} - H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper. ## Claims ### Claim 1 A programmable logic device (PLD) comprising: a power transistor; a programmable fabric; a memory block including one or more lookup tables storing pre-calculated data; and a signal wrapper providing signals between the programmable fabric and the memory block; wherein the pre-populated data stored in the one or more lookup tables of the memory block is programmably changed by programming the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper, wherein the memory block is configured to receive an error signal from the signal wrapper, look up a matching pre-calculated data corresponding to the error signal, and generate a compensated output signal using the matching pre-calculated data, and wherein the compensated output signal is a pulse width of a pulse-width modulation (PWM) signal for driving the power transistor. ### Claim 2 (depends on 1) The PLD of claim 1, wherein the error signal is a digital signal that is converted from an analog error signal using an analog-to-digital converter (ADC). ### Claim 3 (depends on 1) The PLD of claim 1, wherein the pre-calculated data stored in the one or more lookup tables is a product of the error signal multiplied by a constant. ### Claim 4 (depends on 1) The PLD of claim 1, wherein the power transistor is configured as a regulator. ### Claim 5 (depends on 4) The PLD of claim 4, wherein the regulator is one of a buck regulator, a boost regulator, a multiphase buck regulator, a buck-boost regulator, a source side regulator, a drain-side regulator, a push-pull DDR regulator, a load switch, and a battery charger. ### Claim 6 (depends on 1) The PLD of claim 1, wherein the programmable fabric includes a digital fabric, and wherein the compensated output signal is fed to the power transistor via the digital fabric of the programmable fabric. ### Claim 7 (depends on 1) The PLD of claim 1, wherein the PWM signal is fed to a digital filter. ### Claim 8 (depends on 7) The PLD of claim 7, wherein an interactive user interface is provided to a user to adjust one or more gains of the digital filter. ### Claim 9 (depends on 8) The PLD of claim 8, wherein a phase margin and a crossover frequency are interactively adjusted by adjusting the one or more gains of the digital filter. ### Claim 10 (depends on 1) The PLD of claim 1, further comprising a current-sensing comparator block, wherein the compensated output signal is provided to the current-sensing comparator block to drive the power transistor. ### Claim 11 (depends on 10) The PLD of claim 10, wherein the power transistor is turned off using the current-sensing comparator block when a sensed current reaches a programmable threshold value. ### Claim 12 (depends on 11) The PLD of claim 11, wherein the programmable threshold value is modifiable using a programmable slope compensation ramp. ### Claim 13 (depends on 1) The PLD of claim 1, wherein the pre-calculated data stored in the one or more lookup tables is non-linear data corresponding to the error signal. ### Claim 14 (depends on 1) The PLD of claim 1, wherein the error signal is a positive error signal, and the memory block generates the compensated output signal corresponding to a negative error signal by obtaining 2's complement of the pre-calculated data. ### Claim 15 (depends on 1) The PLD of claim 1, wherein the memory block shifts the pre-calculated data by a shifting bit to cover a broader range of the error signal using the one or more lookup tables. ### Claim 16 (depends on 1) The PLD of claim 1, wherein the memory block clips the compensated output signal between a minimum value and a maximum value using a register. ### Claim 17 (depends on 1) The PLD of claim 1, wherein a data width of the pre-calculated data stored in the one or more lookup tables is adjustable to change precision and accuracy of the compensated output signal. ### Claim 18 (depends on 1) The PLD of claim 1, wherein the pre-calculated data stored in the one or more lookup tables are output data corresponding to a selectable response. ### Claim 19 (depends on 1) The PLD of claim 1, wherein the one or more lookup tables include a first lookup table corresponding to a first range of the error signal and a second lookup table corresponding to a second range of the error signal, wherein the first range is narrower than the second range. ### Claim 20 (depends on 1) The PLD of claim 1, further comprising a dynamic clocking system configured to reduce a delay between the error signal and the compensated output signal using a flip-flop that contains a last-stage computed value. ### Claim 21 (depends on 1) The PLD of claim 1, further comprising one or more compensation memory blocks that store the one or more lookup tables, wherein the one or more compensation memory blocks are cascaded to generate the compensated output signal of a higher order.