# US 10,320,390 B1 · Field programmable gate array including coupled lookup tables

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,320,390 B1
- Document ID: US10320390B1
- Status: Granted
- Kind: B1
- Application number: 15/810,496
- Filed: 2017-11-13
- Granted: 2019-06-11
- Earliest claimed: 2016-11-17
- Applicants: X Development LLC
- Inventors: Jonathan Ross
- Web page: https://patentgrep.com/patent/US10320390B1

## CPC

- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/17744: {for input/output signals}
- H03K 19/1776: for memories
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A reconfigurable field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.

## Claims

### Claim 1

A reconfigurable field programmable gate array (FPGA) comprising:
a first logic block comprising a first lookup table; and
a second logic block comprising a second lookup table, wherein the first logic block is coupled to the second logic block,
wherein the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second lookup table of the second logic block,
wherein the first lookup table of the first logic block is coupled to the second lookup table of the second logic block, and
wherein the first lookup table comprises a plurality of first memory cells, the second lookup table comprises a plurality of second memory cells, each first memory cell of the first lookup table corresponds to a respective second memory cell of the second lookup table and is coupled to the corresponding second memory cell of the second lookup table.

### Claim 2 (depends on 1)

The reconfigurable FPGA of claim 1, wherein, for each first memory cell of the first lookup table coupled to a corresponding second memory cell of the second lookup table, a data output of the first memory cell is coupled to a data input of the second memory cell.

### Claim 3 (depends on 1)

The reconfigurable FPGA of claim 1, wherein the plurality of first memory cells and the plurality of second memory cells comprise flip-flop registers.

### Claim 4 (depends on 1)

The reconfigurable FPGA of claim 1, wherein the plurality of first memory cells and the plurality of second memory cells comprise static random access memory (SRAM) elements.

### Claim 5 (depends on 1)

The reconfigurable FPGA of claim 1, wherein the plurality of first memory cells and the plurality of second memory cells comprise CMOS-based memory elements.

### Claim 6 (depends on 1)

The reconfigurable FPGA of claim 1, wherein each first memory cell of the first lookup table and each second memory cell of the second lookup table comprises a corresponding clock input terminal tied to a same clock signal source.

### Claim 7 (depends on 1)

The reconfigurable FPGA of claim 1, wherein the first lookup table of the first logic block is configured to receive a lookup table configuration from a memory component.

### Claim 8

A reconfigurable field programmable gate array (FPGA) comprising:
N total logic blocks arranged in an array, N being an integer greater than 1, and each logic block of the N total logic blocks comprising a respective different lookup table,
wherein, for N−1 logic blocks of the N total logic blocks, each logic block of the N−1 logic blocks is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration to an adjacent logic block within the array, and
wherein, for each lookup table of each logic block of the N total logic blocks, the lookup table comprises a plurality of memory cells.

### Claim 9 (depends on 8)

The reconfigurable FPGA of claim 8, wherein, for the N−1 logic blocks of the N total logic blocks, each logic block of the N−1 logic blocks is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration from the lookup table of the logic block to the lookup table of the adjacent logic block.

### Claim 10 (depends on 8)

The reconfigurable FPGA of claim 8, wherein the plurality of memory cells comprise flip-flop registers.

### Claim 11 (depends on 8)

The reconfigurable FPGA of claim 8, wherein the plurality of memory cells comprise static random access memory (SRAM) elements.

### Claim 12 (depends on 8)

The reconfigurable FPGA of claim 8, wherein each memory cell of the plurality of memory cells comprises a corresponding clock input terminal tied to a same clock signal source.

### Claim 13

A method of updating a lookup table configuration across logic blocks of a reconfigurable field programmable gate array (FPGA), the method comprising:
receiving, at a first logic block of the FPGA, a clock pulse;
upon receiving the clock pulse, receiving, from a second logic block of the FPGA, a first lookup table configuration;
upon receiving the clock pulse, transmitting, to a third logic block of the FPGA, a second lookup table configuration; and
storing the first lookup table configuration in the first logic block,
wherein the second lookup table configuration is transmitted to the third logic block before the first lookup table configuration is stored in the first logic block.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first lookup table configuration is stored in a lookup table of the first logic block.

### Claim 15 (depends on 13)

The method of claim 13, wherein the first lookup table configuration is received from a lookup table of the second logic block.