Static state control of a digital logic circuit within an integrated circuit during low power mode

An integrated circuit, comprising:

• a digital logic circuit having a first transistor and a second transistor;
• a replica circuit having a first transistor and a second transistor which replicate the first transistor and second transistor of the digital logic circuit, and a plurality of switches, wherein the replica circuit is configured into an evaluation configuration when the plurality of switches are in a first configuration and an ageing configuration when the plurality of switches are in a second configuration;
• a storage circuit configured to store a static state indicator;
• a comparison circuit having a first input coupled to the first transistor of the replica circuit, a second input coupled to the second transistor of the replica circuit, and an output coupled to provide the static state indicator to the storage circuit;
• and
• a multiplexer (MUX) having a first data input, a second data input, a control input, and an output, wherein the output is coupled to an input of the digital logic circuit and an input of the replica circuit, the first data input signal is coupled to receive the static state indicator and the second data input is coupled to receive a clock signal, wherein the MUX is configured to provide the first data input as the output of the MUX during a low power mode and to provide the second data input as the output of the MUX during a high power mode.

In an integrated circuit having a digital logic circuit with a first transistor and a second transistor, and a replica circuit with a first transistor and a second transistor which replicate the first transistor and second transistor of the digital logic circuit, a method comprises:

• during a high power mode, providing a run mode signal to an input of the digital logic circuit and an input of the replica circuit;
• during a low power mode, providing a static state indicator instead of the run mode signal to the input of the digital logic circuit and the input of the replica circuit,
• wherein when the replica circuit is configured into an ageing configuring, the first transistor and second transistor of the replica circuit experience a same stress as the first transistor and second transistor of the digital logic circuit, and
• wherein when the replica circuit is configured into an evaluation configuration, a threshold voltage of the first transistor of the replica circuit is compared to threshold voltage of the second transistor, and a result of the comparison is stored in storage circuitry as the static state indicator.