# US 10,320,386 B1 · Programmable pipeline interface circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,320,386 B1
- Document ID: US10320386B1
- Status: Granted
- Kind: B1
- Application number: 15/836,571
- Filed: 2017-12-08
- Published: 2019-06-13
- Granted: 2019-06-11
- Earliest claimed: 2017-12-08
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Ilya K. Ganusov; Brian C. Gaide; Henri Fraisse
- Web page: https://patentgrep.com/patent/US10320386B1

## CPC

- H03K 19/00323: {Delay compensation}
- H03K 3/037: Bistable circuits
- H03K 19/017581: {programmable}
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- H03K 19/1774: {for global signals, e.g. clock, reset}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

## Claims

### Claim 1

A circuit arrangement comprising:
a logic circuit;
a first plurality of bi-stable circuits, each bi-stable circuit of the first plurality having a data input, a clock input, and an output coupled to the logic circuit;
control circuitry coupled to the first plurality of bi-stable circuits, wherein the control circuitry is programmable to:
receive an input clock signal;
selectively connect, responsive to a first plurality of control signals, outputs of the first plurality of bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit,
generate one or more delayed clock signals from the input clock signal, and
selectively provide, responsive to a second plurality of control signals, one of the one or more delayed clock signals or the input clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

### Claim 2 (depends on 1)

The circuit arrangement of claim 1, wherein the control circuitry is further configured to:
generate a plurality of alternative clock signals from the input clock signal; and
select, for input to the clock input of each of the first plurality of bi-stable circuits, one clock signal of the plurality of alternative clock signals.

### Claim 3 (depends on 1)

The circuit arrangement of claim 1, wherein the control circuitry includes:
a first clock path including a delay circuit coupled to receive the input clock signal and configured to generate one of the one or more delayed clock signals, and a first pulse generator coupled to receive the one of the delayed clock signals from the delay circuit, wherein the pulse generator is configured to reduce a pulse width of the one of the delayed clock signals and output a first clock signal;
a second clock path includes a second pulse generator coupled to receive the input clock signal, wherein the pulse generator is configured to reduce a pulse width of the input clock signal and output a second clock signal; and
wherein the control circuitry is further configured to select, for input to the clock input of each of the first plurality of bi-stable circuits, the first clock signal or the second clock signal.

### Claim 4 (depends on 1)

The circuit arrangement of claim 1, further comprising:
a second plurality of bi-stable circuits, each bi-stable circuit of the second plurality having a clock input and a data input coupled to receive an output signal of the logic circuit; and
wherein the control circuitry is further programmable to selectively provide the one of the one or more delayed clock signals or the input clock signal without delay to the clock input of each of the second plurality of bi-stable circuits.

### Claim 5 (depends on 4)

The circuit arrangement of claim 4, wherein the control circuitry is further programmable to selectively supply the input clock signal having a first pulse width to the first plurality of bi-stable circuits or supply the input clock signal having a second pulse width to the first plurality of bi-stable circuits and to the second plurality of bi-stable circuits, wherein the first pulse width is narrower than the second pulse width.

### Claim 6 (depends on 1)

The circuit arrangement of claim 1, wherein the control circuitry includes:
a first clock path including a first delay circuit coupled to receive the input clock signal and configured to generate one of the one or more delayed clock signals, and a first pulse generator coupled to receive the one of the one or more delayed clock signals from the first delay circuit, wherein the first pulse generator is configured to reduce a pulse width of the delayed clock signal and output a first clock signal;
a second clock path includes a second pulse generator coupled to receive the input clock signal, wherein the second pulse generator is configured to reduce a pulse width of the input clock signal and output a second clock signal;
a third clock path including a third pulse generator coupled to receive the input clock signal, wherein the third pulse generator is configured to reduce a pulse width of the delayed clock signal and output a third clock signal having a pulse width greater than a pulse width of the first clock signal; and
wherein the control circuitry is further configured to select, for input to the clock input of each of the first plurality of bi-stable circuits, the first clock signal, the second clock signal, or the third clock signal.

### Claim 7 (depends on 6)

The circuit arrangement of claim 6, wherein the second clock path includes:
an inverter coupled to receive the input clock signal and output an inverted clock signal; and
a multiplexer coupled to receive the inverted clock signal and the input clock signal, wherein the multiplexer is configured to select the inverted clock signal or the input clock signal for input to the second pulse generator.

### Claim 8 (depends on 1)

The circuit arrangement of claim 1, wherein the first plurality of bi-stable circuits are level-sensitive latches.

### Claim 9 (depends on 1)

The circuit arrangement of claim 1, wherein:
the control circuitry includes for each input to the logic circuit, a respective data selection circuit that is programmable independent of each other respective data selection circuit to selectively connect the output of a bi-stable circuit of the first plurality of bi-stable circuits or the signal at the data input the bi-stable circuit to an input of the logic circuit; and
the control circuitry includes for each of the first plurality of bi-stable circuits, a respective clock selection circuit that is programmable independent of each other respective clock selection circuit to selectively provide the one of the one or more delayed clock signals or the input clock signal without delay to the clock input of the bi-stable circuit.

### Claim 10 (depends on 1)

The circuit arrangement of claim 1, wherein the first plurality of bi-stable circuits are edge-triggered flip-flops.

### Claim 11

A circuit arrangement, comprising:
a plurality of blocks of programmable logic circuitry, wherein each block of programmable logic circuitry is configurable to implement a logic function;
programmable interconnect circuitry that is configurable to selectively route signals between the plurality of blocks of programmable logic;
a plurality of interface circuits coupled to the plurality of blocks of programmable logic circuitry, respectively, wherein each interface circuit includes:
a first plurality of bi-stable circuits, each bi-stable circuit of the first plurality having a data input, a clock input, and an output coupled to the respective block of programmable logic circuitry;
control circuitry coupled to the first plurality of bi-stable circuits, wherein the control circuitry is programmable to:
receive an input clock signal;
selectively connect, responsive to a first plurality of control signals, outputs of the first plurality of bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the respective block of programmable logic circuitry,
generate one or more delayed clock signals from the input clock signal, and
selectively provide, responsive to a second plurality of control signals, one of the one or more delayed clock signals or the input clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

### Claim 12 (depends on 11)

The circuit arrangement of claim 11, wherein the control circuitry is further configured to:
generate a plurality of alternative clock signals from the input clock signal; and
select, for input to the clock input of each of the first plurality of bi-stable circuits, one clock signal of the plurality of alternative clock signals.

### Claim 13 (depends on 11)

The circuit arrangement of claim 11, wherein the control circuitry includes:
a first clock path including a delay circuit coupled to receive the input clock signal and configured to generate one of the one or more delayed clock signals, and a first pulse generator coupled to receive the one of the delayed clock signals from the delay circuit, wherein the pulse generator is configured to reduce a pulse width of the one of the delayed clock signals and output a first clock signal;
a second clock path includes a second pulse generator coupled to receive the input clock signal, wherein the pulse generator is configured to reduce a pulse width of the input clock signal and output a second clock signal; and
wherein the control circuitry is further configured to select, for input to the clock input of each of the first plurality of bi-stable circuits, the first clock signal or the second clock signal.

### Claim 14 (depends on 11)

The circuit arrangement of claim 11, further comprising:
a second plurality of bi-stable circuits, each bi-stable circuit of the second plurality having a clock input and a data input coupled to receive an output signal of the logic circuit; and
wherein the control circuitry is further programmable to selectively provide the one of the one or more delayed clock signals or the input clock signal without delay to the clock input of each of the second plurality of bi-stable circuits.

### Claim 15 (depends on 14)

The circuit arrangement of claim 14, wherein the control circuitry is further programmable to selectively supply the input clock signal having a first pulse width to the first plurality of bi-stable circuits or supply the input clock signal having a second pulse width to the first plurality of bi-stable circuits and to the second plurality of bi-stable circuits, wherein the first pulse width is narrower than the second pulse width.

### Claim 16 (depends on 11)

The circuit arrangement of claim 11, wherein the control circuitry includes:
a first clock path including a first delay circuit coupled to receive the input clock signal and configured to generate one of the one or more delayed clock signals, and a first pulse generator coupled to receive the one of the one or more delayed clock signals from the first delay circuit, wherein the first pulse generator is configured to reduce a pulse width of the delayed clock signal and output a first clock signal;
a second clock path includes a second pulse generator coupled to receive the input clock signal, wherein the second pulse generator is configured to reduce a pulse width of the input clock signal and output a second clock signal;
a third clock path including a third pulse generator coupled to receive the input clock signal, wherein the third pulse generator is configured to reduce a pulse width of the delayed clock signal and output a third clock signal having a pulse width greater than a pulse width of the first clock signal; and
wherein the control circuitry is further configured to select, for input to the clock input of each of the first plurality of bi-stable circuits, the first clock signal, the second clock signal, or the third clock signal.

### Claim 17 (depends on 16)

The circuit arrangement of claim 16, wherein the second clock path includes:
an inverter coupled to receive the input clock signal and output an inverted clock signal; and
a multiplexer coupled to receive the inverted clock signal and the input clock signal, wherein the multiplexer is configured to select the inverted clock signal or the input clock signal for input to the second pulse generator.

### Claim 18 (depends on 11)

The circuit arrangement of claim 11, wherein the first plurality of bi-stable circuits are level-sensitive latches.

### Claim 19 (depends on 11)

The circuit arrangement of claim 11, wherein:
the control circuitry includes for each input to the logic circuit, a respective data selection circuit that is programmable independent of each other respective data selection circuit to selectively connect the output of a bi-stable circuit of the first plurality of bi-stable circuits or the signal at the data input the bi-stable circuit to an input of the logic circuit; and
the control circuitry includes for each of the first plurality of bi-stable circuits, a respective clock selection circuit that is programmable independent of each other respective clock selection circuit to selectively provide the one of the one or more delayed clock signals or the input clock signal without delay to the clock input of the bi-stable circuit.

### Claim 20 (depends on 11)

The circuit arrangement of claim 11, wherein the first plurality of bi-stable circuits are edge-triggered flip-flops.