# US 10,320,381 B2 · Reduced VSWR switching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,381 B2 - Document ID: US10320381B2 - Status: Granted - Kind: B2 - Application number: 14/671,785 - Filed: 2015-03-27 - Published: 2016-09-29 - Granted: 2019-06-11 - Earliest claimed: 2015-03-27 - Assignees: Integrated Device Technology, Inc. - Applicants: Kathiravan Krishnamurthi; Jean-Marc Mourant; Olivier Hubert; Shawn Bawell - Inventors: Kathiravan Krishnamurthi; Jean-Marc Mourant; Olivier Hubert; Shawn Bawell - Web page: https://patentgrep.com/patent/US10320381B2 ## CPC - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H03K 17/165: {by feedback from the output circuit to the control circuit} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch. ## Claims ### Claim 1 A device comprising: a switch configured to mitigate variation in switch impedance during a switch transition from a start state to an end state by stepping the switch a plurality of times through a sequence of steps during the switch transition that step the switch through a sequence of different states from the start state to at least one intermediate state to the end state, wherein the start and end states are static states of the switch and the at least one intermediate state is at least one non-static transitional state of the switch. ### Claim 2 (depends on 1) The device of claim 1, wherein the at least one intermediate state comprises a first intermediate state and a second intermediate state. ### Claim 3 (depends on 1) The device of claim 1, the switch comprising a first branch and a second branch, wherein stepping the switch through the sequence of different states from the start state to the at least one intermediate state to the end state comprises: stepping the first branch through a first branch sequence of different states from a first branch start state to at least one first branch intermediate state to a first branch end state; and stepping the second branch through a second branch sequence of different states from a second branch start state to at least one second branch intermediate state to a second branch end state. ### Claim 4 (depends on 3) The device of claim 3, wherein the second branch sequence is a reverse order of the first branch sequence. ### Claim 5 (depends on 1) The device of claim 1, wherein at least one of the step from the start state to the at least one intermediate state and the step from the at least one intermediate state to the end state comprises a reconfiguration of the switch. ### Claim 6 (depends on 5) The device of claim 5, the switch comprising a plurality of switch elements, wherein the reconfiguration of the switch comprises at least one of opening and closing at least one of the plurality of switch elements. ### Claim 7 (depends on 6) The device of claim 6, the switch comprising a first branch selectable to couple a first input to a first output of the switch, the plurality of switch elements comprising at least one series switch and at least one shunt switch in the first branch. ### Claim 8 (depends on 7) The device of claim 7, wherein the at least one series switch comprises a first series switch and a second series switch between the first input and the first output and the at least one shunt switch comprises a first shunt switch in a first shunt path and a second shunt switch in a second shunt path. ### Claim 9 (depends on 8) The device of claim 8, the at least one intermediate state comprising a first intermediate state and a second intermediate state, wherein the switch is configured for a first transition from a first start state to a first end state as follows: the first start state comprises the first branch configured with the first and second shunt switches closed and the first and second series switches open; the first intermediate state comprises the first branch configured with the first shunt switch open, the second shunt switch closed and the first and second series switches open; the second intermediate state comprises the first branch configured with the first shunt switch open, the second shunt switch closed and the first and second series switches closed; and the first end state comprises the first branch configured with the first and second shunt switches open and the first and second series switches closed. ### Claim 10 (depends on 6, 9) The device of claim 6, wherein the switch is configured for a second transition from a second start state to a second end state comprising a reverse order of states in claim 9. ### Claim 11 A method comprising: mitigating variation in switch impedance during a switch transition from a start state to an end state by: stepping the switch a plurality of times through a sequence of steps during the switch transition that step the switch through a sequence of different states from the start state to at least one intermediate state to the end state, wherein the start and end states are static states of the switch and the at least one intermediate state is at least one non-static transitional state of the switch. ### Claim 12 (depends on 11) The method of claim 11, further comprising: receiving a control signal; and generating from the control signal a first sequence of switch control signals for a first switch transition that steps the switch through a first sequence of different states from a first start state to at least one intermediate state to a first end state. ### Claim 13 (depends on 12) The method of claim 12, further comprising: generating a second sequence of switch control signals for a second switch transition that steps the switch through a second sequence of different states from a second start state to at least one intermediate state to a second end state by: selecting a different order of switch control signals for the first sequence of switch control signals. ### Claim 14 (depends on 11) The method of claim 11, wherein stepping the switch through a sequence of different states from the start state to at least one intermediate state to the end state comprises: stepping the switch from the start state to a first intermediate state; stepping the switch from the first intermediate state to a second intermediate state; and stepping the switch from the second intermediate state to the end state. ### Claim 15 (depends on 11) The method of claim 11, the switch comprising a first branch and a second branch, wherein stepping the switch through a sequence of different states from the start state to at least one intermediate state to the end state comprises: stepping the first branch through a first branch sequence of different states from a first branch start state to at least one first branch intermediate state to a first branch end state; and stepping, the second branch through a second branch sequence of different states from a second branch start state to at least one second branch intermediate state to a second branch end state. ### Claim 16 (depends on 15) The method of claim 15, wherein a first step in the first branch sequence switches a first load impedance into the first branch and wherein a final step in the second branch sequence switches a second load impedance out of the second branch. ### Claim 17 (depends on 16) The method of claim 16, wherein the switch transition comprises selecting the second branch and deselecting the first branch. ### Claim 18 A device comprising: a switch controller configured to mitigate variation in switch impedance during a switch transition from a start state to an end state by stepping the switch a plurality of times through a sequence of steps during the switch transition that step the switch through a sequence of different states from the start state to at least one intermediate state to the end state, wherein the start and end states are static states of the switch and the at least one intermediate state is at least one non-static transitional state of the switch. ### Claim 19 (depends on 18) The device of claim 18, the switch controller comprising a first branch controller, wherein, for the switch transition, the first branch controller is configured to transition a first branch of the switch between a selected (ON) state and a deselected (OFF) state by stepping the first branch of the switch through a sequence of different states from a first branch start state to at least one first branch intermediate state to a first branch end state. ### Claim 20 (depends on 18) The device of claim 18, wherein the first branch controller is configured to transition the first branch of the switch from ON to OFF states with at least one intermediate state and from OFF to ON states with at least one intermediate state in response to a one bit control signal.