# US 10,320,380 B2 · Power circuit and power module using MISFET having control circuit disposed between gate and source > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,380 B2 - Document ID: US10320380B2 - Status: Granted - Kind: B2 - Application number: 15/724,491 - Filed: 2017-10-04 - Published: 2018-02-15 - Granted: 2019-06-11 - Earliest claimed: 2013-12-26 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Hirotaka Otake; Tatsuya Yanagi; Yusuke Nakakohara - Web page: https://patentgrep.com/patent/US10320380B2 ## CPC - H03K 17/162: {without feedback from the output circuit to the control circuit} - H03K 17/04106: {in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence)} - H03K 17/165: {by feedback from the output circuit to the control circuit} - H10D 12/031: {of IGBTs} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/8325: {Silicon carbide} - H10D 84/144: {in antiparallel diode configurations} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/40: Leadframes - H10W 70/421: {Shapes or dispositions} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/465: {Bumps or wires} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 76/60: Seals - H10W 90/00: Package configurations - H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate. ## Claims ### Claim 1 A power circuit comprising: a main substrate comprising a front side surface and a back side surface; a first wiring pattern disposed on the front side surface of the main substrate; a second wiring pattern disposed on the front side surface of the main substrate; a first MISFET of which a first drain is disposed on the first electrode pattern, the first MISFET comprising a source electrode and a gate electrode on an upper surface thereof; a third wiring pattern disposed on the front side surface of the main substrate, the third wiring pattern electrically connected to the gate electrode; and a fourth wiring pattern disposed on the front side surface of the main substrate, the fourth wiring pattern electrically connected to the source electrode, wherein a first control circuit configured to control a current path conducted towards the gate electrode from the source electrode is disposed between the third wiring pattern and the fourth wiring pattern. ### Claim 2 (depends on 1) The power circuit according to claim 1, further comprising a connecting means configured to electrically connect the source electrode and the second wiring pattern. ### Claim 3 (depends on 1) The power circuit according to claim 1, wherein the first MISFET is configured to connect a plurality of chips in parallel, and the third wiring pattern and the fourth wiring pattern are wiring patterns configured to commonly connect each of the chips of the first MISFET. ### Claim 4 (depends on 1) The power circuit according to claim 1, wherein external terminals extending from each electrode on the main substrate to an outside of the main substrate are respectively connected to the first to fourth wiring patterns. ### Claim 5 (depends on 1) The power circuit according to claim 1, further comprising a shield layer inserted in an inside of each of the first to fourth wiring patterns or inserted between each of the first to fourth wiring patterns and the main substrate. ### Claim 6 (depends on 1) The power circuit according to claim 1, further comprising: a fifth wiring pattern disposed on the front side surface of the main substrate; a second MISFET which is disposed on the 2nd above-mentioned wiring pattern, the second MISFET comprising a source electrode and a gate electrode on an upper surface thereof; a sixth wiring pattern disposed on the front side surface of the main substrate, the sixth wiring pattern electrically connected to the gate electrode of the second MISFET; and a seventh wiring pattern disposed on the front side surface of the main substrate, the seventh wiring pattern electrically connected to the source electrode of the second MISFET. ### Claim 7 (depends on 6) The power circuit according to claim 6, further comprising a second control circuit configured to control a current path conducted towards the gate electrode from the source electrode, the second control circuit disposed between the six wiring pattern and the seventh wiring pattern. ### Claim 8 (depends on 1) The power circuit according to claim 1, further comprising: a snubber capacitor connected between the first wiring pattern and the fifth wiring pattern. ### Claim 9 (depends on 1) The power circuit according to claim 1, wherein the first MISFET is a wideband-gap type power semiconductor device. ### Claim 10 (depends on 6) The power circuit according to claim 6, wherein the second MISFET is a wideband-gap type power semiconductor device. ### Claim 11 (depends on 4) The power circuit according to claim 4, further comprising: a package configured to seal at least a part of each external terminal, the first MISFET, the control circuit, and the connecting means. ### Claim 12 (depends on 1) The power circuit according to claim 1, wherein the first control circuit comprises a first gated diode of which a first cathode is connected to a first gate of the first MISFET and a first anode is connected to the first source of the first MISFET. ### Claim 13 (depends on 7) The power circuit according to claim 7, wherein the second control circuit comprises a second gated diode of which a second cathode is connected to the second gate of the second MISFET, and a second anode is connected to the second source of the second MISFET. ### Claim 14 (depends on 1) The power circuit according to claim 1, wherein the first control circuit comprises a third MISFET of which a third drain is connected to the first gate, and a third source is connected to the first source. ### Claim 15 (depends on 7) The power circuit according to claim 7, wherein the second control circuit comprises a fourth MISFET of which a fourth drain is connected to the second gate, and a fourth source is connected to the second source. ### Claim 16 (depends on 1) The power circuit according to claim 1, further comprising: a first signal substrate on which the third wiring pattern and the fourth wiring pattern are mounted. ### Claim 17 (depends on 1) The power circuit according to claim 1, wherein the first control circuit comprises an first gated diode connected between the third wiring pattern and the fourth wiring pattern. ### Claim 18 (depends on 1) The power circuit according to claim 1, wherein the first control circuit comprises a third MISFET connected between the third wiring pattern and the fourth wiring pattern. ### Claim 19 (depends on 18) The power circuit according to claim 18, wherein the power circuit comprises a first gate capacitor for applying gate-negative bias, the first gate capacitor connected between a source of the third MISFET and a source sense of the first MISFET. ### Claim 20 (depends on 7) The power circuit according to claim 7, wherein the second control circuit comprises a fourth MISFET connected between the sixth wiring pattern and the seventh wiring pattern, and the power circuit comprises a second gate capacitor for applying gate-negative bias, the second gate capacitor connected between a source of the fourth MISFET and a source sense of the second MISFET. ### Claim 21 (depends on 12) The power circuit according to claim 12, wherein a circuit constant is set up so that a forward voltage when the first gated diode is conducting becomes lower than a negative-side absolute maximum rating of a voltage between the gate and the source in the first MISFET. ### Claim 22 (depends on 21) The power circuit according to claim 21, wherein the first gated diode is a diode selected from the group consisting of a Zener diode and a Schottky barrier diode. ### Claim 23 (depends on 16) The power circuit according to claim 16, further comprising: a shield for shielding a radiation noise between an inside of the first signal substrate or the main substrate, and the first signal substrate. ### Claim 24 (depends on 6) The power circuit according to claim 6, wherein one selected from the group consisting of the first MISFET and the second MISFET comprises an SiC MISFET. ### Claim 25 (depends on 6) The power circuit according to claim 6, wherein one selected from the group consisting of the first MISFET and the second MISFET comprises an SiC Trench MISFET. ### Claim 26 A power module comprising a power circuit, wherein the power circuit comprises: a main substrate comprising a front side surface and a back side surface; a first wiring pattern disposed on the front side surface of the main substrate, the first wiring pattern connected to a first terminal; a second wiring pattern disposed on the front side surface of the main substrate, the third wiring pattern connected to a second terminal; a first MISFET of which a first drain is disposed on the first electrode pattern, the first MISFET comprising a source electrode and a gate electrode on an upper surface thereof; a third wiring pattern disposed on the front side surface of the main substrate, the third wiring pattern electrically connected to the gate electrode; and a fourth wiring pattern disposed on the front side surface of the main substrate, the fourth wiring pattern electrically connected to the source electrode, wherein a first control circuit configured to control a current path conducted towards the gate electrode from the source electrode is disposed between the third wiring pattern and the fourth wiring pattern, wherein the power module further comprising external terminals configured to respectively extend signals of the third and fourth wiring patterns to an outside of the main substrate. ### Claim 27 (depends on 26) The power module according to claim 26, wherein the power module except for at least a part of each terminal is sealed with a thermosetting resin. ### Claim 28 (depends on 26) The power module according to claim 26, wherein the first gated diode is disposed nearer to a semiconductor chip side than a mounting position of a signal terminal of the fourth wiring pattern on the main substrate. ### Claim 29 (depends on 26) The power module according to claim 26, wherein the first terminal and the third terminal are disposed at a first side of the main substrate, the output terminal is disposed at a third side opposite to the first side, a signal terminal of the first control circuit is disposed at a second side adjacent to the first side, and a signal terminal of the second control circuit is disposed at a fourth side opposite to the second side. ### Claim 30 (depends on 26) A converter comprising a plurality of power modules according to claim 26. ### Claim 31 (depends on 26) An inverter comprising a plurality of power modules according to claim 26. ### Claim 32 A semiconductor device, comprising: a die substrate comprising a front side surface and a back side surface, the die substrate further comprising a first external terminal; an MISFET of which a drain is disposed on the front side surface of the die substrate, the MISFET comprising a source electrode and a gate electrode on the upper surface thereof; a second external terminal disposed so as to be adjacent to the first external terminal, the second external terminal electrically connected to the source electrode; a third external terminal disposed so as to be adjacent to the first external terminal, the third external terminal electrically connected to the gate electrode; a control circuit of which an anode electrode is disposed on the second external terminal, and a cathode electrode disposed on the upper surface thereof; a connecting means configured to electrically connect the third external terminal with the cathode electrode; and a package configured to seal at least a part of each external terminal, the first MISFET, and the connecting means. ### Claim 33 (depends on 32) The semiconductor device according to claim 32, wherein the anode electrode of the control circuit is disposed on one end of the second external terminal, and the cathode electrode of the control circuit is electrically connected to an one end of the third external terminal. ### Claim 34 (depends on 32) The semiconductor device according to claim 32, wherein an anode electrode of the control circuit is disposed on the source electrode, and the cathode electrode of the control circuit is electrically connected to an one end of the third external terminal. ### Claim 35 (depends on 32) The semiconductor device according to claim 32, wherein the control circuit comprises a gated diode. ### Claim 36 (depends on 35) The semiconductor device according to claim 35, wherein a circuit constant is set up so that a forward voltage when the gated diode is conducting becomes lower than a negative-side absolute maximum rating of a voltage between the gate and the source in the MISFET. ### Claim 37 (depends on 35) The semiconductor device according to claim 35, wherein the gated diode is a diode selected from the group consisting of a Zener diode and a Schottky barrier diode. ### Claim 38 (depends on 32) A converter comprising a plurality of the semiconductor devices according to claim 32 used as a switching element. ### Claim 39 (depends on 32) An inverter comprising a plurality of the semiconductor devices according to claim 32 used as a switching element. ### Claim 40 A power module comprising: a main substrate comprising a front side surface; a first wiring pattern disposed on the front side surface of the main substrate; a second wiring pattern disposed on the front side surface of the main substrate; a first MISFET of which a first drain is disposed on the first wiring pattern, the first MISFET comprising a source electrode and a gate electrode on an upper surface thereof; a first pillar connection electrode electrically connected to the source electrode of the first MISFET; a plate electrode electrically connected to the first pillar connection electrode; and a gate control conductive portion electrically connected between the gate electrode of the first MISFET and the second wiring pattern. ### Claim 41 (depends on 40) The power module according to claim 40, wherein the gate control conductive portion is a wire. ### Claim 42 (depends on 41) The power module according to claim 41, wherein the plate electrode is electrically connected to a source lead terminal of the power module. ### Claim 43 (depends on 42) The power module according to claim 42, wherein a conductive material is provided between the first wiring pattern and the first MISFET. ### Claim 44 (depends on 43) The power module according to claim 43, wherein a conductive material is provided between the first pillar connection electrode and the source electrode of the first MISFET. ### Claim 45 (depends on 44) The power module according to claim 44, wherein a height of the wire is not higher than a height of the plate electrode. ### Claim 46 (depends on 45) The power module according to claim 45, wherein the first wiring pattern and the second wiring pattern are isolated electrically. ### Claim 47 (depends on 46) The power module according to claim 46, wherein the first wiring pattern is electrically connected to a drain lead terminal. ### Claim 48 (depends on 47) The power module according to claim 47, wherein both of the source lead terminal and the drain lead terminal are protruding in opposite directions from one another. ### Claim 49 (depends on 48) The power module according to claim 48, further comprising: a second MISFET having a source electrode and a gate electrode; a second pillar connection electrode; a third wiring pattern disposed on the front side surface of the main substrate; wherein the second pillar connection electrode is electrically connected to the source electrode of the second MISFET, and the second MISFET is electrically connected to the third wiring pattern. ### Claim 50 (depends on 49) The power module according to claim 49, wherein both of the first MISFET and the second MISFET are controlled in a manner so that a same voltage potential is provided to the gate electrode of the first MISFET and to the gate electrode of the second MISFET.