# US 10,320,376 B2 · Frequency divider with selectable frequency and duty cycle

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- Number: US 10,320,376 B2
- Document ID: US10320376B2
- Status: Granted
- Kind: B2
- Application number: 15/347,050
- Filed: 2016-11-09
- Published: 2018-05-10
- Granted: 2019-06-11
- Earliest claimed: 2016-11-09
- Assignees: Integrated Device Technology, Inc.
- Applicants: Integrated Device Technologies, Inc.
- Inventors: Richard Geiss
- Web page: https://patentgrep.com/patent/US10320376B2

## CPC

- H03K 5/1565: {the output pulses having a constant duty cycle}
- H03K 21/026: {comprising logic circuits}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors. The pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor.

## Claims

### Claim 1

A frequency divider system comprising:
a split-divisor frequency divider module that receives a clock signal and generates an output signal based on a first divisor and a second divisor, the clock signal and output signal each having rectangular waveforms characterized by a respective frequency and pulse width;
wherein:
the frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors;
the pulse width of the output signal is a selectable integer number of clock cycles of the clock signal, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor;
a fractional pulse width adjuster module, the fractional pulse width adjuster module is configured to adjust the pulse width of a split-divisor frequency divider module output signal by a fraction of an input clock cycle; and
a high frequency bypass module, the high frequency bypass module configured to bypass one or more stages of the frequency divider,
wherein the split-divisor frequency divider module comprises:
a selector module configured to select between the first and second divisors based on a control input, the control input being coupled to the output signal of the split-divisor frequency divider module;
an integer divider configured to generate pulses every N2 clock cycles, where N2 is set to one of the first and second divisors selected by the selector module; and
a toggle module configured to toggle the output signal at each low-to-high or high-to-low transition of the pulses generated by the integer divider.

### Claim 2

A frequency divider system comprising:
a split-divisor frequency divider module that receives a clock signal and generates an output signal based on a first divisor and a second divisor, the clock signal and output signal each having rectangular waveforms characterized by a respective selectable frequency and a selectable pulse width;
wherein:
the frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors;
the pulse width of the output signal is a selectable integer number of clock cycles of the clock signal, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor; and
wherein the split-divisor frequency divider module comprises:
a selector module configured to select between the first and second divisors based on a control input, the control input being coupled to the output signal of the split-divisor frequency divider module;
an integer divider configured to generate pulses every N2 clock cycles, where N2 is set to one of the first and second divisors selected by the selector module; and
a toggle module configured to toggle the output signal at each low-to-high or high-to-low transition of the pulses generated by the integer divider.

### Claim 3 (depends on 2)

The frequency divider system of claim 2, wherein the frequency of the output signal is 1/N times the frequency of the clock signal, where N is the sum of the first and second divisors.

### Claim 4 (depends on 2)

The frequency divider system of claim 2, wherein the pulse width of the output signal is N0 or N1 clock cycles, where N0 and N1 are the first and second divisors, respectively.

### Claim 5 (depends on 2)

The frequency divider system of claim 2, wherein the selector module includes a multiplexer.

### Claim 6 (depends on 2)

The frequency divider system of claim 2, wherein the toggle module includes a flip-flop.

### Claim 7 (depends on 2)

The frequency divider system of claim 2, further comprising a fractional pulse width adjuster module that adjusts the pulse width of the output signal by a fraction of the clock cycle of the clock signal based on an adjuster control signal.

### Claim 8 (depends on 7)

The frequency divider system of claim 7, wherein the fractional pulse width adjuster module lengthens or shortens the pulse width of the output signal by half of the clock cycle of the clock signal.

### Claim 9 (depends on 8)

The frequency divider system of claim 8, wherein the adjuster control signal is a Boolean enable/disable signal that is high when the sum of the first and second divisors is odd and low when the sum of the first and second divisors is even.

### Claim 10 (depends on 8)

The frequency divider system of claim 8, wherein the fractional pulse width adjuster module comprises:
a flip-flop circuit that receives an inverted version of the clock signal at a clock input node and the output signal of the split-divisor frequency divider module at a D input node; and
a Boolean logic gate that performs a logic operation based on the output signal of the split-divisor frequency divider module and a second output signal of the flip-flop circuit.

### Claim 11 (depends on 10)

The frequency divider system of claim 10, wherein the logic operation is selected from a group consisting of: AND, OR, NAND, and NOR.

### Claim 12 (depends on 2)

The frequency divider system of claim 2, further comprising a high frequency bypass module that bypasses one or more portions of the frequency divider system to increase the frequency of the output signal above a maximum frequency of the split-divisor frequency divider.

### Claim 13 (depends on 12)

The frequency divider system of claim 12, wherein the maximum frequency of the split-divisor frequency divider is ¼ times the frequency of the clock signal.