# US 10,320,375 B2 · SoC supply droop compensation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,375 B2 - Document ID: US10320375B2 - Status: Granted - Kind: B2 - Application number: 15/640,922 - Filed: 2017-07-03 - Published: 2018-03-01 - Granted: 2019-06-11 - Earliest claimed: 2016-07-01 - Assignees: Chaoyang Semiconductor Jiangyin Technology Co., Ltd. - Applicants: Endura Technologies LLC - Inventors: Hassan Ihs - Web page: https://patentgrep.com/patent/US10320375B2 ## CPC - H03K 5/15: Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00) - G01R 19/165: Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values - G01R 19/16552: {in I.C. power supplies} - G05F 1/565: sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) - G05F 3/08: wherein the variable is DC - H02M 3/155: using semiconductor devices only - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K 2005/00019: {Variable delay} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract Droop monitors spread across a system-on-chip (SoC) monitor for voltage droops in regulated supply voltage supplied to logic circuitry of the SoC. In the event of a voltage droop, a clock signal supplied to the logic circuitry is stretched, to temporarily increase a period of the clock signal. The droop monitors may include a sensing delay line provided voltage at the regulated supply voltage, and a reference delay line supplied with a reference voltage, with operations of the delay lines monitored to determine a voltage droop. ## Claims ### Claim 1 A system for compensating for voltage droops in power supplied to integrated circuitry, comprising: a plurality of droop monitors within an integrated circuit, the droop monitors configured to detect occurrence of a droop in voltage level below a specified level of a regulated supply voltage; and clock adjustment circuitry configured to stretch a period of a clock signal supplied to portions of the integrated circuit in response to detection of the occurrence of the droop in voltage level below the specified level; wherein the droop monitors are configured to monitor a speed of execution of sensing integrated circuitry compared to speed of execution of reference integrated circuitry; wherein the sensing integrated circuitry comprises a sensing delay line and the reference integrated circuitry comprises a reference delay line; wherein the droop monitors include a lock loop to set a delay of the sensing delay line to a predetermined delay. ### Claim 2 (depends on 1) The system of claim 1, wherein the sensing delay line and the reference delay line each comprise a digital delay line. ### Claim 3 (depends on 1) The system of claim 1, wherein the predetermined delay covers a clock cycle of a system clock signal. ### Claim 4 (depends on 1) The system of claim 1, wherein the droop monitors include a tuning loop to tune a delay of the reference delay line to a delay of the sensing delay line. ### Claim 5 (depends on 1) The system of claim 1, further comprising a low dropoff regulator to provide power to the reference integrated circuitry at a first voltage level and a DC-DC switching regulator to provide power to the sensing integrated circuitry is provided power at a regulated supply voltage level. ### Claim 6 (depends on 1) The system of claim 1, wherein the clock adjustment circuitry is configured to select a system clock signal at a particular phase from a plurality of clock signals each having different phases. ### Claim 7 (depends on 6) The system of claim 6, wherein the clock adjustment circuitry is configured to stretch a period of the system clock signal supplied to portions of the integrated circuit by selecting a next to be used clock signal that is phase delayed compared to a currently used clock signal. ### Claim 8 A system for compensating for voltage droops in power supplied to integrated circuitry, comprising: a plurality of droop monitors within an integrated circuit, the droop monitors configured to detect occurrence of a droop in voltage level below a specified level of a regulated supply voltage; and clock adjustment circuitry configured to stretch a period of a clock signal supplied to portions of the integrated circuit in response to detection of the occurrence of the droop in voltage level below the specified level; wherein the droop monitors are configured to monitor a speed of execution of sensing integrated circuitry compared to speed of execution of reference integrated circuitry; wherein the sensing integrated circuitry comprises a sensing delay line and the reference integrated circuitry comprises a reference delay line; wherein the droop monitors include a tuning loop to tune a delay of the reference delay line to a delay of the sensing delay line. ### Claim 9 (depends on 8) The system of claim 8, wherein the sensing delay line and the reference delay line each comprise a digital delay line. ### Claim 10 (depends on 8) The system of claim 8, wherein the droop monitors include a lock loop to set a delay of the sensing delay line to a predetermined delay. ### Claim 11 (depends on 10) The system of claim 10, wherein the predetermined delay covers a clock cycle of a system clock signal. ### Claim 12 (depends on 8) The system of claim 8, further comprising a low dropoff regulator to provide power to the reference integrated circuitry at a first voltage level and a DC-DC switching regulator to provide power to the sensing integrated circuitry is provided power at a regulated supply voltage level. ### Claim 13 (depends on 8) The system of claim 8, wherein the clock adjustment circuitry is configured to select a system clock signal at a particular phase from a plurality of clock signals each having different phases. ### Claim 14 (depends on 13) The system of claim 13, wherein the clock adjustment circuitry is configured to stretch a period of the system clock signal supplied to portions of the integrated circuit by selecting a next to be used clock signal that is phase delayed compared to a currently used clock signal.