# US 10,320,369 B2 · Sequential circuits and operating methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,369 B2 - Document ID: US10320369B2 - Status: Granted - Kind: B2 - Application number: 15/903,507 - Filed: 2018-02-23 - Published: 2018-06-28 - Granted: 2019-06-11 - Earliest claimed: 2015-09-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyunchul Hwang; Minsu Kim - Web page: https://patentgrep.com/patent/US10320369B2 ## CPC - H03K 3/356121: {with synchronous operation (H03K3/35613, H03K3/356147 take precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence) - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock. ## Claims ### Claim 1 A sequential circuit, comprising: a first stage configured to charge a voltage of a first node in response to a clock and to discharge the voltage of the first node in response to the clock and a logic signal; a second stage configured to charge a voltage of a second node in response to the clock and to maintain a state of charge at the second node based on the logic signal and to discharge the voltage of the second node in response to the clock and the logic signal; a combinational logic configured to generate the logic signal using the voltage of the first node, the voltage of the second node, and data; and a latch circuit configured to latch the voltage of the second node in response to the clock, wherein the combinational logic generates the logic signal such that the voltage of the second node is not discharged when the voltage of the first node is discharged or such that the voltage of the first node is not discharged when the voltage of the second node is discharged. ### Claim 2 (depends on 1) The sequential circuit of claim 1, wherein the first stage comprises: a first PMOS transistor configured to connect the first node to a power supply terminal in response to the clock; a second PMOS transistor configured to connect the first node to the power supply terminal in response to the voltage of the second node; and a first NMOS transistor configured to connect a first connection node to the first node in response to the clock. ### Claim 3 (depends on 2) The sequential circuit of claim 2, wherein the second stage comprises: a first PMOS transistor configured to connect the second node to the power supply terminal in response to the clock; a second PMOS transistor configured to connect the second node to the power supply terminal in response to the logic signal; a first NMOS transistor having one end connected to the second node in response to the logic signal; and a second NMOS transistor configured to connect a ground terminal to other end of the first NMOS transistor of the second stage in response to the clock, wherein the first connection node is connected to a gate terminal of the first NMOS transistor of the second stage. ### Claim 4 (depends on 2) The sequential circuit of claim 2, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; and an AND-OR-Inverter (AOI) gate configured to receive the voltage of the second node, the data, and an output value of the inverter and to generate the logic signal. ### Claim 5 (depends on 4) The sequential circuit of claim 4, wherein the AOI gate comprises: a first NMOS transistor having one end connected to the second node in response to the logic signal; and a second NMOS transistor configured to connect a ground terminal to other end of the first NMOS transistor of the AOI gate in response to the clock. ### Claim 6 (depends on 1) The sequential circuit of claim 1, wherein the latch circuit comprises: a first PMOS transistor configured to connect an output node to a power supply terminal in response to the voltage of the second node; a first NMOS transistor having one end connected to the output node in response to the clock; a second NMOS transistor configured to connect other end of the first NMOS transistor of the latch circuit to a ground terminal in response to the voltage of the second node; and a buffer configured to buffer a voltage of the output node. ### Claim 7 (depends on 6) The sequential circuit of claim 6, wherein the latch circuit further comprises: an inverter configured to invert the voltage of the output node. ### Claim 8 (depends on 1) The sequential circuit of claim 1, wherein the first stage comprises: a first PMOS transistor having one end connected to the first node in response to the clock; a second PMOS transistor configured to connect the first node to a power supply terminal in response to the voltage of the second node; a third PMOS transistor configured to connect other end of the first PMOS transistor of the first stage to the power supply terminal in response to a scan input; a fourth PMOS transistor configured to connect the one end of the first PMOS transistor of the first stage to the power supply terminal in response to a scan enable signal; a first NMOS transistor configured to connect a first connection node to the first node in response to the clock; a second NMOS transistor having one end connected to the first node in response to the scan input; a third NMOS transistor having one end connected to other end of the second NMOS transistor of the first stage in response to the scan enable signal; and a fourth NMOS transistor configured to connect other end of the third NMOS transistor of the first stage to a ground terminal in response to the voltage of the second node, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; and an AOI gate configured to receive an output value of the inverter, an inverted scan enable signal, the voltage of the second node, and the data and to generate the logic signal, and wherein the first connection node is connected to an output terminal of the AOI gate. ### Claim 9 (depends on 1) The sequential circuit of claim 1, wherein the first stage comprises: a first PMOS transistor configured to connect the first node to a power supply terminal in response to the clock, a second PMOS transistor configured to connect the first node to the power supply terminal in response to the voltage of the second node, and a first NMOS transistor configured to connect a first connection node to the first node in response to the clock, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node, a multiplexer configured to select one of the data or a scan input in response to a scan enable signal, and an AOI gate configured to receive an output value of the multiplexer, the voltage of the second node, and an output value of the inverter and to generate the logic signal, and wherein the first connection node is connected to an output terminal of the AOI gate. ### Claim 10 (depends on 1) The sequential circuit of claim 1, wherein the first stage comprises: a first PMOS transistor having one end connected to the first node in response to the clock; a second PMOS transistor configured to connect the first node to a power supply terminal in response to the voltage of the second node; a third PMOS transistor configured to connect other end of the first PMOS transistor of the first stage to the power supply terminal in response to a scan input; a fourth PMOS transistor configured to connect the one end of the first PMOS transistor of the first stage to the power supply terminal in response to a scan enable signal; a first NMOS transistor configured to connect a first connection node to the first node in response to the clock; a second NMOS transistor having one end connected to the first node in response to the scan input; and a third NMOS transistor configured to connect a second connection node to other end of the second NMOS transistor of the first stage in response to the scan enable signal, and wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; a first PMOS transistor having one end connected to the first connection node in response to an output value of the inverter; a second PMOS transistor configured to connect other end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the data; a third PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to an inverted scan enable signal; a fourth PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the voltage of the second node; a first NMOS transistor configured to connect a ground terminal to the first connection node in response to the output value of the inverter, a second NMOS transistor having one end connected to the first connection node in response to the data; a third NMOS transistor configured to connect other end of the second NMOS transistor of the combinational logic to the second connection node in response to the inverted scan enable signal; and a fourth NMOS transistor configured to connect the ground terminal to the second connection node in response to the voltage of the second node. ### Claim 11 A sequential circuit, comprising: a first stage comprising: a first PMOS transistor having one end connected to a first node in response to a clock, a second PMOS transistor configured to connect the first node to a power supply terminal in response to a voltage of a second node, a third PMOS transistor configured to connect other end of the first PMOS transistor to the power supply terminal in response to a scan input, a fourth PMOS transistor configured to connect the one end of the first PMOS transistor to the power supply terminal in response to a scan enable signal, a first NMOS transistor configured to connect a first connection node to the first node in response to the clock, a second NMOS transistor having one end connected to the first node in response to the scan input, and a third NMOS transistor configured to connect a second connection node to other end of the second NMOS transistor in response to the scan enable signal; a second stage comprising: a first PMOS transistor configured to connect the second node to the power supply terminal in response to the clock, a second PMOS transistor configured to connect the second node to the power supply terminal in response to a logic signal, a first NMOS transistor connected to the second node in response to the logic signal, and a second NMOS transistor configured to connect a ground terminal to other end of the first NMOS transistor of the second stage in response to the clock; a combinational logic configured to receive data, the voltage of the first node, and the voltage of the second node and to generate the logic signal, wherein an output terminal of the combinational logic outputting the logic signal is connected to the first connection node; and a latch circuit configured to latch the voltage of the second node in response to the clock. ### Claim 12 (depends on 11) The sequential circuit of claim 11, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; a first PMOS transistor having one end connected to the first connection node in response to an output value of the inverter; a second PMOS transistor configured to connect other end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the data; a third PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to an inverted version of the scan enable signal; a fourth PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the voltage of the second node; a first NMOS transistor configured to connect the ground terminal to the first connection node in response to the output value of the inverter; a second NMOS transistor having one end connected to the first connection node in response to the data; a third NMOS transistor configured to connect other end of the second NMOS transistor of the combinational logic to the second connection node in response to the inverted version of the scan enable signal; and a fourth NMOS transistor configured to connect the ground terminal to the second connection node in response to the voltage of the second node. ### Claim 13 (depends on 11) The sequential circuit of claim 11, wherein the second stage further comprises: a third PMOS transistor configured to connect the one end of the first PMOS transistor of the second stage to the power supply terminal in response to a reset signal and to connect one end of the second PMOS transistor of the second stage to the power supply terminal in response to the reset signal; and a third NMOS transistor configured to connect the ground terminal to the second node in response to the reset signal. ### Claim 14 (depends on 11) The sequential circuit of claim 11, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; a first PMOS transistor having one end connected to the first connection node in response to an output value of the inverter; a second PMOS transistor configured to connect other end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the data; a third PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to an inverted version of the scan enable signal; a fourth PMOS transistor configured to connect the first connection node to the power supply terminal in response to the voltage of the second node; a first NMOS transistor configured to connect the ground terminal to the first connection node in response to the output value of the inverter; a second NMOS transistor having one end connected to the first connection node in response to the data; a third NMOS transistor configured to connect other end of the second NMOS transistor of the combinational logic to the second connection node in response to the inverted version of the scan enable signal; and a fourth NMOS transistor configured to connect the ground terminal to the second connection node in response to the voltage of the second node. ### Claim 15 (depends on 11) The sequential circuit of claim 11, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; a first PMOS transistor having one end connected to the first connection node in response to an output value of the inverter; a second PMOS transistor configured to connect other end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the data; a third PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to an inverted version of the scan enable signal; a fourth PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the voltage of the second node; a first NMOS transistor configured to connect the second connection node to the first connection node in response to the output value of the inverter; a second NMOS transistor having one end connected to the first connection node in response to the data; a third NMOS transistor configured to connect other end of the second NMOS transistor of the combinational logic to the second connection node in response to the inverted version of the scan enable signal; and a fourth NMOS transistor configured to connect the ground terminal to the second connection node in response to the voltage of the second node. ### Claim 16 (depends on 11) The sequential circuit of claim 11, wherein the combinational logic comprises: an inverter configured to invert the voltage of the first node; a first PMOS transistor having one end connected to the first connection node in response to an output value of the inverter; a second PMOS transistor configured to connect other end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the data; a third PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to an inverted version of the scan enable signal; a fourth PMOS transistor configured to connect the first connection node to the power supply terminal in response to the voltage of the second node; a first NMOS transistor configured to connect the second connection node to the first connection node in response to the output value of the inverter; a second NMOS transistor having one end connected to the first connection node in response to the data; a third NMOS transistor configured to connect other end of the second NMOS transistor of the combinational logic to the second connection node in response to the inverted version of the scan enable signal; and a fourth NMOS transistor configured to connect the ground terminal to the second connection node in response to the voltage of the second node. ### Claim 17 A sequential circuit, comprising: a first stage comprising: a first PMOS transistor configured to connect a first node to a power supply terminal in response to a clock, a second PMOS transistor configured to connect the first node to the power supply terminal in response to a voltage of a second node, and a first NMOS transistor configured to connect a first connection node to the first node in response to the clock; a second stage comprising: a first PMOS transistor configured to connect the second node to the power supply terminal in response to the clock, a second PMOS transistor configured to connect the second node to the power supply terminal in response to a logic signal, a first NMOS transistor having one end connected to the second node in response to the logic signal, and a second NMOS transistor configured to connect a ground terminal to other end of the first NMOS transistor of the second stage in response to the clock; a combinational logic comprising: an inverter configured to invert the voltage of the second node, an AOI gate configured to receive an output value of the inverter, the voltage of the second node, and data and to generate the logic signal; and a latch circuit configured to latch the voltage of the second node in response to the clock. ### Claim 18 (depends on 17) The sequential circuit of claim 17, wherein the first connection node is connected to an output terminal of the AOI gate. ### Claim 19 (depends on 17) The sequential circuit of claim 17, further comprising: a discharge circuit configured to discharge the voltage of the first node between the first connection node and the ground terminal. ### Claim 20 (depends on 17) The sequential circuit of claim 17, further comprising: an inverter configured to invert an output value of the latch circuit.