# US 10,320,368 B2 · Ring oscillator circuit and clock signal generation circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,368 B2 - Document ID: US10320368B2 - Status: Granted - Kind: B2 - Application number: 15/446,391 - Filed: 2017-03-01 - Published: 2017-09-14 - Granted: 2019-06-11 - Earliest claimed: 2016-03-11 - Assignees: Seiko Epson Corporation - Applicants: Seiko Epson Corporation - Inventors: Koichi Hatanaka - Web page: https://patentgrep.com/patent/US10320368B2 ## CPC - H03K 3/0315: {Ring oscillators} - H03K 3/00: Circuits for generating electric pulses; Monostable, bistable or multistable circuits (H03K4/00 takes precedence; for digital function generators in computers G06F1/02) - H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} - H03L 1/028: {of generators comprising piezoelectric resonators (H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32)} - H03L 1/04: Constructional details for maintaining temperature constant - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A ring oscillator circuit includes a plurality of first delay circuits each including X first delay elements, and a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X≥1. ## Claims ### Claim 1 A ring oscillator circuit comprising: a plurality of first delay circuits each including X first delay elements; a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, wherein the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X≥1; and a plurality of switches, each of the plurality of switches having a first node and a second node, wherein the first node of each of the plurality of switches is connected to an output of each first delay circuit in a subset of the plurality of first delay circuits, and the second node of each of the plurality of switches is connected to an input of the each of the plurality of second delay circuits. ### Claim 2 (depends on 1) The ring oscillator circuit according to claim 1, wherein the second delay circuit is singly provided. ### Claim 3 (depends on 1) The ring oscillator circuit according to claim 1, wherein the plurality of second delay elements has respective delay amounts, which are no smaller than 1 time and no larger than 2 times of a delay amount of the first delay element, and are different from each other. ### Claim 4 (depends on 1) The ring oscillator circuit according to claim 1, wherein the plurality of second delay elements is respectively formed of field-effect transistors different in gate length from each other. ### Claim 5 (depends on 1) The ring oscillator circuit according to claim 1, wherein the plurality of second delay elements is respectively formed of field-effect transistors different in gate width from each other. ### Claim 6 (depends on 1) A clock signal generation circuit comprising: the ring oscillator circuit according to claim 1; and a control section adapted to alternatively select the second delay element to be loaded among the plurality of second delay elements in accordance with a given clock signal so that the ring oscillator circuit generates a clock signal in accordance with the given clock signal. ### Claim 7 (depends on 6) The clock signal generation circuit according to claim 6, wherein the second delay circuit is singly provided. ### Claim 8 (depends on 6) The clock signal generation circuit according to claim 6, wherein the plurality of second delay elements has respective delay amounts, which are no smaller than 1 time and no larger than 2 times of a delay amount of the first delay element, and are different from each other. ### Claim 9 (depends on 6) The clock signal generation circuit according to claim 6, wherein the plurality of second delay elements is respectively formed of field-effect transistors different in gate length from each other. ### Claim 10 (depends on 6) The clock signal generation circuit according to claim 6, wherein the plurality of second delay elements is respectively formed of field-effect transistors different in gate width from each other. ### Claim 11 A ring oscillator circuit comprising: a plurality of first delay circuits each including X first delay elements; a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, wherein the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X≥1; a plurality of first switches, each of the plurality of first switches having a first node and a second node, wherein the first node of each of the plurality of first switches is connected to an output of each first delay circuit in a subset of the plurality of first delay circuits, and the second node of each of the plurality of switches is connected to an input of the each of the plurality of second delay circuits; and a plurality of second switches, each of the plurality of second having a first node and a second node, wherein the first node of each of the plurality of second switches is connected to an input of a first delay circuit of the plurality of first delay circuits, and the second node of each of the plurality of second switches is connected to an input of each of the plurality of second delay circuits.