# US 10,320,345 B2 · Amplifier architecture using positive envelope feedback

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- Number: US 10,320,345 B2
- Document ID: US10320345B2
- Status: Granted
- Kind: B2
- Application number: 15/862,914
- Filed: 2018-01-05
- Published: 2018-07-12
- Granted: 2019-06-11
- Earliest claimed: 2017-01-06
- Assignees: Skyworks Solutions, Inc.
- Applicants: Skyworks Solutions, Inc.
- Inventors: Smarjeet Sharma; Nicolas Gerard Constantin
- Web page: https://patentgrep.com/patent/US10320345B2

## CPC

- H03F 3/195: in integrated circuits
- H03F 1/0222: {by using a signal derived from the input signal}
- H03F 1/0272: {by using a signal derived from the output signal}
- H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers}
- H03F 1/0294: {using vector summing of two or more constant amplitude phase-modulated signals}
- H03F 1/565: {using inductive elements}
- H03F 3/245: {with semiconductor devices only}
- H03F 3/45188: {Non-folded cascode stages}
- H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F 2200/102: A non-specified detector of a signal envelope being used in an amplifying circuit
- H03F 2200/111: the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2203/45481: the CSC comprising only a direct connection to the supply voltage, no other components being present
- H03F 2203/7209: the gated amplifier being switched from a first band to a second band
- H03F: AMPLIFIERS

## Abstract

Described herein are power amplifier (PA) architectures that improve PA performance (e.g., efficiency, linearity, etc.) over an extended range of the operating power levels of the PA. These architectures can be implemented on a single chip to provide a single-chip standalone PA solution. This improvement comes with little additional complexity, little additional current consumption, and/or little additional chip area. The architectures utilize a dynamic biasing technique using positive envelope feedback based at least in part on an instantaneous envelope signal at an output of a power amplifier.

## Claims

### Claim 1

A power amplifier architecture comprising:
a multi-stage amplifier having an input port and an output port, the multi-stage amplifier to receive an input signal at the input port and to provide an amplified output signal at the output port;
an envelope detector coupled to the output port of the multi-stage amplifier, the envelope detector configured to receive a signal corresponding to the amplified output signal and to generate an envelope signal related to an envelope of the amplified output signal; and
a dynamic bias signal generator coupled to the envelope detector and to the multi-stage amplifier, the dynamic bias signal generator configured to receive the envelope signal from the envelope detector and to scale the envelope signal using a voltage divider, to receive a DC signal, to generate a dynamic bias signal related to the envelope of the amplified output signal with the DC signal being used to offset the scaled envelope signal to generate the dynamic bias signal, and to provide the dynamic bias signal to the multi-stage amplifier.

### Claim 2 (depends on 1)

The power amplifier architecture of claim 1 wherein the power amplifier architecture is implemented on a single chip.

### Claim 3 (depends on 1)

The power amplifier architecture of claim 1 wherein the DC signal corresponds to a quiescent biasing condition of the multi-stage amplifier.

### Claim 4 (depends on 1)

The power amplifier architecture of claim 1 wherein the multi-stage amplifier includes a driver stage coupled to the input port and a power stage coupled to the output port.

### Claim 5 (depends on 4)

The power amplifier architecture of claim 4 wherein the dynamic bias signal is used to bias a transistor of the power stage.

### Claim 6 (depends on 1)

The power amplifier architecture of claim 1 wherein the envelope detector is configured to detect signals that span an expected range of amplitudes of the amplified output signal.

### Claim 7 (depends on 1)

The power amplifier architecture of claim 1 wherein a loop gain is less than or equal to 0 dB, the loop gain including a gain of an up-conversion gain through the multi-stage amplifier and a gain of a signal path through the envelope detector and the dynamic bias signal generator.

### Claim 8 (depends on 7)

The power amplifier architecture of claim 7 wherein the loop gain is less than or equal to −3 dB.

### Claim 9 (depends on 1)

The power amplifier architecture of claim 1 wherein a loop bandwidth is at least four times higher than a bandwidth of the envelope of the amplified output signal.

### Claim 10 (depends on 1)

The power amplifier architecture of claim 1 wherein the envelope signal generated by the envelope detector corresponds to an instantaneous output power of the multi-stage amplifier.

### Claim 11 (depends on 1)

The power amplifier architecture of claim 1 wherein the power amplifier architecture is implemented using CMOS or GaAs technologies.

### Claim 12 (depends on 1)

The power amplifier architecture of claim 1 wherein the power amplifier architecture is implemented on a single chip and does not use signal processing provided by a component that is not on the single chip to determine the envelope signal or to determine the dynamic bias signal.

### Claim 13

A radio-frequency (RF) module comprising:
a packaging substrate configured to receive a plurality of components; and
a power amplification system implemented on the packaging substrate, the power amplification system including a multi-stage amplifier configured to provide an amplified output signal having an envelope, an envelope detector configured to detect the envelope of the amplified output signal, and a resistive voltage shifter configured to generate a dynamic bias signal related to the detected envelope of the amplified output signal and to provide the dynamic bias signal to the multi-stage amplifier.

### Claim 14 (depends on 13)

The RF module of claim 13 wherein the RF module is a front-end module (FEM).

### Claim 15 (depends on 13)

The RF module of claim 13 wherein the multi-stage amplifier, the envelope detector, and the resistive voltage shifter are implemented on a single chip.

### Claim 16

A wireless device comprising:
a transceiver configured to generate an input radio-frequency (RF) signal;
a front-end module (FEM) in communication with the transceiver, the FEM including a packaging substrate configured to receive a plurality of components, the FEM further including a power amplification system implemented on the packaging substrate, the power amplification system configured to amplify the input RF signal to generate an amplified output RF signal, the power amplification system including a multi-stage amplifier configured to provide the amplified output signal having an envelope, an envelope detector configured to detect the envelope of the amplified output signal, and a resistive voltage shifter configured to generate a dynamic bias signal related to the detected envelope of the amplified output signal and to provide the dynamic bias signal to the multi-stage amplifier; and
an antenna in communication with the FEM, the antenna configured to transmit the output RF signal.

### Claim 17 (depends on 16)

The wireless device of claim 16 wherein the resistive voltage shifter includes a voltage divider to scale the detected envelope.

### Claim 18 (depends on 17)

The wireless device of claim 17 wherein the dynamic bias signal biases a gate of a transistor of the multi-stage amplifier.

### Claim 19

A power amplifier architecture comprising:
a multi-stage amplifier having an input port and an output port, the multi-stage amplifier to receive an input signal at the input port and to provide an amplified output signal at the output port;
an envelope detector coupled to the output port of the multi-stage amplifier, the envelope detector configured to receive a signal corresponding to the amplified output signal and to generate an envelope signal related to an envelope of the amplified output signal; and
a dynamic bias signal generator coupled to the envelope detector and to the multi-stage amplifier, the dynamic bias signal generator configured to receive the envelope signal from the envelope detector, to generate a dynamic bias signal related to the envelope of the amplified output signal, and to provide the dynamic bias signal to the multi-stage amplifier, with a loop gain of the architecture being less than or equal to 0 dB, the loop gain including a gain of an up-conversion gain through the multi-stage amplifier and a gain of a signal path through the envelope detector and the dynamic bias signal generator.

### Claim 20 (depends on 19)

The power amplifier architecture of claim 19 wherein the loop gain is less than or equal to −3 dB.