# US 10,320,293 B1 · Cycle skipping prevent circuit in a regulator of a DC-to-DC converter

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- Number: US 10,320,293 B1
- Document ID: US10320293B1
- Status: Granted
- Kind: B1
- Application number: 16/179,978
- Filed: 2018-11-04
- Published: 2019-07-04
- Granted: 2019-06-11
- Earliest claimed: 2017-12-30
- Assignees: Active-Semi, Inc.
- Applicants: Active-Semi, Inc.
- Inventors: Masashi Nogawa
- Web page: https://patentgrep.com/patent/US10320293B1

## CPC

- H02M 3/157: with digital control
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 1/44: Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
- H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators
- H02M 3/158: including plural semiconductor devices as final control devices for a single load
- H02M 1/0009: {Devices or circuits for detecting current in a converter}
- H02M 3/1566: {with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A DC-to-DC converter employs peak current mode control and includes a cycle skipping prevent circuit. If a latch is set, then a high side switch is turned on. A comparator receives a signal indicative of current flow and a compensated error signal. The prevent circuit supplies a delayed version of a low duty cycle, fixed frequency, oscillator signal onto the set input lead of the latch. The prevent circuit gates a high signal as output by the comparator onto the reset input lead of the latch. If the output of the comparator has, however, not transitioned high by a predetermined time, then the prevent circuit gates a high pulse onto the reset input lead. Accordingly, the prevent circuit ensures that the latch is reset once every period of the signal SET. A cycle skipping prevent circuit is also disclosed for use in a converter that employs valley current mode control.

## Claims

### Claim 1

A method comprising:
(a) outputing a voltage signal VCURRENT from a current sense circuit, wherein the voltage signal VCURRENT is indicative of a magnitude of a current;
(b) receiving the voltage signal VCURRENT onto an input lead of a comparator circuit;
(c) outputing a RESET0 signal onto an output lead of the comparator circuit;
(d) receiving the RESET0 signal and an oscillator signal OSC onto a cycle skipping prevent circuit;
(e) supplying a delayed version of the oscillator signal OSC onto a set input lead of a sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET;
(f) receiving a cycle skipping prevent enable signal onto the cycle skipping prevent circuit, wherein the cycle skipping prevent enable signal is a single-bit digital signal; and
(g) using the cycle skipping prevent circuit to gate a digital logic high signal as output by the comparator circuit onto a reset input lead of the sequential logic element if the RESET0 signal is at a digital logic high level, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the cycle skipping prevent circuit gates a high pulse onto the reset input lead of the sequential logic element, wherein if the cycle skipping prevent enable signal has a first digital logic level then the cycle skipping prevent circuit is enabled to gate a high pulse onto the set input lead of the sequential logic element in (g) if the RESET0 signal has not transitioned to the digital logic high level by the predetermined time in the period, wherein if the cycle skipping prevent enable signal has a second digital logic level then the cycle skipping prevent circuit is disabled from gating a high pulse onto the set input lead of the sequential logic element in (g) if the RESET0 signal has not transitioned to the digital logic high level by the predetermined time in the period.

### Claim 2 (depends on 1)

The method of claim 1, wherein (a) through (g) are performed while a voltage regulator control circuit is controlling a DC-to-DC switching converter using a peak current (PC) mode.

### Claim 3 (depends on 2)

The method of claim 2, wherein the sequential logic element, the current sense circuit, the comparator circuit, and the cycle skipping prevent circuit are parts of the voltage regulator control circuit.

### Claim 4 (depends on 1)

The method of claim 1, wherein the cycle skipping prevent circuit gates the high pulse onto the reset input lead of the sequential logic element in (g) such that the digital logic high level on the reset input lead then returns to a digital logic low level before the end of the period.

### Claim 5 (depends on 1)

The method of claim 1, wherein the predetermined time is a time of an edge of the oscillator signal OSC.

### Claim 6 (depends on 1)

The method of claim 1, wherein the cycle skipping prevent circuit includes a digital logic gate that has an input lead and an output lead, wherein the digital logic gate receives the RESET0 signal onto its input lead, and wherein of the digital logic gate is coupled to the reset input lead of the sequential logic element.

### Claim 7 (depends on 1)

The method of claim 1, wherein the cycle skipping prevent circuit includes a delay element that receives the oscillator signal OSC and that supplies the signal SET onto the set input lead of the sequential logic element.

### Claim 8 (depends on 1)

The method of claim 1, wherein the cycle skipping prevent circuit includes a flip-flop having a clock input lead and a data input lead, wherein the data input lead of the flip-flop is coupled to an output lead of the sequential logic element, and wherein the oscillator signal OSC is supplied onto the clock input lead of the flip-flop.

### Claim 9 (depends on 1)

The method of claim 1, wherein the oscillator signal OSC is at the digital logic high level for less than twenty percent of the period, and is at a digital logic low level for more than eighty percent of the period.

### Claim 10 (depends on 1)

The method of claim 1, wherein the sequential logic element is a latch.

### Claim 11 (depends on 1)

The method of claim 1, wherein the comparator circuit receives a compensated error signal VE-C onto another input lead of the comparator circuit.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
(h) controlling a high side switch of a DC-to-DC switching converter with a digital signal output by the sequential logic element.

### Claim 13

A method comprising:
controlling a DC-to-DC switching converter with a voltage regulator control circuit, wherein the voltage regulator control circuit includes a sequential logic element, a comparator circuit, a flip-flop, first logic gate circuitry, second logic gate circuitry, and a delay element, wherein the sequential logic element has a set input lead, a reset input lead, and an output lead, wherein the comparator circuit has a first input lead, a second input lead, and an output lead, wherein the first input lead of the comparator circuit receives a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a current flow in the DC-to-DC switching converter, wherein the flip-flop has an oscillator signal input lead, a data input lead, and a data output lead, wherein the first logic gate circuitry has a first input lead, a second input lead, and an output lead, wherein the second input lead of the first logic gate circuitry is coupled to the data output lead of the flip-flop, wherein the second logic gate circuitry has a first input lead, a second input lead, and an output lead, wherein the second input lead of the second logic gate circuitry is coupled to receive a signal from the output lead of the first logic gate circuitry, wherein the first input lead of the second logic gate circuitry is coupled to receive a signal from the output lead of the comparator circuit, wherein the output lead of the second logic gate circuitry is coupled to supply a signal onto the reset input lead of the sequential logic element, wherein the delay element has an input lead and an output lead, wherein the input lead of the delay element is coupled to receive an oscillator signal, and wherein the output lead of the delay element is coupled to supply a signal onto the set input lead of the sequential logic element.

### Claim 14 (depends on 13)

The method of claim 13, wherein the DC-to-DC switching converter includes a high side switch, and wherein a digital signal output by the sequential logic element onto the output lead of the sequential logic element controls the high side switch.

### Claim 15

A method comprising:
providing a voltage regulator control circuit that controls a DC-to-DC switching converter, wherein the voltage regulator control circuit comprises:
a sequential logic element having a set input lead, a reset input lead, and an output lead;
a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current;
a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives the voltage signal VCURRENT from the current sense circuit, wherein the comparator circuit outputs a RESET0 signal onto the output lead of the comparator circuit;
a signal conductor, wherein an oscillator signal OSC is present on the signal conductor; and
a cycle skipping prevent circuit that receives the RESET0 signal and that receives the oscillator signal OSC, wherein the cycle skipping prevent circuit supplies a delayed version of the oscillator signal OSC onto the set input lead of the sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET, wherein the cycle skipping prevent circuit gates a digital logic high signal as output by the comparator circuit onto the reset input lead of the sequential logic element if the RESET0 signal as output by the comparator circuit is at a digital logic high level, wherein the cycle skipping prevent circuit includes a digital logic gate that has an input lead and an output lead, wherein the digital logic gate receives the RESET0 signal onto its input lead, wherein the output lead of the digital logic gate is coupled to the reset input lead of the sequential logic element, wherein the cycle skipping prevent circuit includes a delay element that receives the oscillator signal OSC and that supplies the signal SET onto the set input lead of the sequential logic element, wherein the cycle skipping prevent circuit includes a flip-flop having a clock input lead and a data input lead, wherein the data input lead of the flip-flop is coupled to the output lead of the sequential logic element, and wherein the oscillator signal OSC is supplied onto the clock input lead of the flip-flop.

### Claim 16 (depends on 15)

The method of claim 15, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the cycle skipping prevent circuit gates a high pulse onto the reset input lead of the sequential logic element.