# US 10,320,285 B2 · One cycle controlled power factor correction circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,320,285 B2 - Document ID: US10320285B2 - Status: Granted - Kind: B2 - Application number: 16/037,267 - Filed: 2018-07-17 - Published: 2019-02-07 - Granted: 2019-06-11 - Earliest claimed: 2017-08-02 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Jintae Kim; Sangcheol Moon - Web page: https://patentgrep.com/patent/US10320285B2 ## CPC - H02M 1/4225: {using a non-isolated boost converter} - H02M 1/0009: {Devices or circuits for detecting current in a converter} - H02M 1/0025: {Arrangements for modifying reference values, feedback values or error values in the control loop of a converter} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A control circuit for controlling a Switch-Mode Power Supply (SMPS) includes a current conduction duration determining circuit, an integrator circuit, a feedback circuit, a sawtooth generator circuit, and a gate control circuit. The current conduction duration determining circuit produces a duration signal according to a duration of a current of the SMPS. The integrator circuit produces an integrator output corresponding to an integral over time of a magnitude of the current. The feedback circuit produces a comparison voltage according to an output voltage of the SMPS. The sawtooth generator circuit produces a sawtooth signal using the comparison voltage and duration signal, such as by dividing the comparison voltage by the duration signal. The gate control circuit generates a gate signal for controlling a power switch of the SMPS according to a comparison of the sawtooth signal to the integrator output. The SMPS may be a Power Factor Correction circuit. ## Claims ### Claim 1 A control circuit comprising: a duration determining circuit to receive a zero crossing detection signal and produce a duration signal using the zero crossing detection signal; an integrator circuit to receive a current sense signal and produce an integrator output corresponding to an integral over a measurement period of the current sense signal; a feedback circuit to receive a feedback signal and produce a comparison signal corresponding to a difference between the feedback signal and a reference voltage; a divider circuit to produce a sawtooth control signal corresponding to a result of dividing the comparison signal by the duration signal; an oscillator circuit to produce a sawtooth signal according to the comparison signal and the sawtooth control signal; and a gate control circuit to produce a reset signal by asserting the reset signal in response to a value of the integrator output being greater than or equal to a value of the sawtooth signal, and to produce a gate signal by de-asserting the gate signal in response to the assertion of the reset signal. ### Claim 2 (depends on 1) The control circuit of claim 1, wherein the control circuit is for controlling a Power Factor Correction (PFC) circuit, wherein: the PFC circuit produces the zero crossing detection signal and current sense signal according to a current through an inductor; the PFC circuit controls the current through the inductor using the gate signal; and the PFC circuit produces the feedback signal according to an output voltage of the PFC circuit. ### Claim 3 (depends on 1) The control circuit of claim 1, wherein the integrator circuit comprises: a capacitor having a first terminal coupled to a ground and a second terminal coupled to the integrator output; a switch coupled across the capacitor and configures to discharge the capacitor in response to the assertion of the reset signal; and a voltage-to-current converter coupled to the second terminal of the capacitor to provide a current to the capacitor according to a value of the current sense signal. ### Claim 4 (depends on 1) The control circuit of claim 1, wherein the duration determining circuit comprises: a ramp generator circuit to reset a ramp voltage in response to an indication that the gate signal is asserted and to increase the ramp voltage at a predetermined rate thereafter; and a sample-and-hold circuit to sample the ramp voltage when the zero crossing detection signal indicates that a current is flowing and to hold and output a previously-sampled value of the ramp voltage when the zero crossing detection signal indicates that the current is not flowing. ### Claim 5 (depends on 1) The control circuit of claim 1, wherein the duration determining circuit comprises: a zero current detection circuit to receive the zero current detection signal and a zero current reference voltage, and to produce a zero current signal by asserting the zero current signal when the zero current detection signal is less than the zero current reference voltage; an edge-triggered flip-flop circuit to generate a charge-discharge signal by asserting the charge-discharge signal when the gate signal is asserted and de-asserting the charge-discharge signal in response to an assertion of the zero current signal; and a low-pass filter to generate the duration signal by averaging a value of the charge-discharge signal. ### Claim 6 (depends on 1) The control circuit of claim 1, wherein the oscillator circuit comprises: a switch circuit to couple the sawtooth signal to the comparison signal in response to an assertion of a set signal; a capacitor having a first terminal coupled to the sawtooth signal and a second terminal coupled to a ground; and a voltage-to-current converter coupled across the capacitor to generate a current for discharging the capacitor at a rate corresponding to a value of the sawtooth control signal, wherein the assertion of the set signal corresponds to an assertion of the gate signal. ### Claim 7 A control circuit for controlling a Switch-Mode Power Supply (SMPS), the control circuit comprising: a current conduction duration determining circuit to produce a duration signal according to a duration of a current of the SMPS; an integrator circuit to produce an integrator output corresponding to an integral over time of a magnitude of the current of the SMPS; a feedback circuit to produce a comparison voltage according to an output voltage of the SMPS; a sawtooth generator circuit to produce a sawtooth signal according to the comparison voltage and the duration signal; and a gate control circuit to generate a gate signal for controlling a power switch of the SMPS according to a comparison of the sawtooth signal and the integrator output. ### Claim 8 (depends on 7) The control circuit of claim 7, wherein the SMPS includes a Power Factor Correction (PFC) circuit. ### Claim 9 (depends on 7) The control circuit of claim 7, wherein the current conduction duration determining circuit receives a zero crossing detection signal from the SMPS and produces the duration signal having a value corresponding to an elapsed time from an assertion of the gate signal to an occurrence of a zero current indication on the zero crossing detection signal. ### Claim 10 (depends on 7) The control circuit of claim 7, wherein the integrator circuit resets the integrator output in response to a de-assertion of the gate signal. ### Claim 11 (depends on 7) The control circuit of claim 7, wherein the sawtooth generator circuit sets the sawtooth to a value according to the comparison signal in response to an assertion of the gate signal, and subsequently decreases a magnitude of the sawtooth signal at a rate corresponding to a result of dividing the comparison voltage and the duration signal. ### Claim 12 (depends on 7) The control circuit of claim 7, wherein the gate control circuit de-asserts the gate signal in response to the integrator output being equal to or greater than the sawtooth signal. ### Claim 13 (depends on 7) The control circuit of claim 7, wherein the control circuit performs single-cycle average-current-mode control of the SMPS. ### Claim 14 A method for controlling a Switched Mode Power Supply (SMPS) circuit, the method comprising: producing, by an integrator circuit, an integrator output corresponding to an integral over the duration of a measurement cycle of a value of a current sense signal, the current sense signal indicating a current of the SMPS circuit; producing, by a duration determining circuit, a duration signal corresponding to a duration of the current of the SMPS circuit; producing, by an oscillator circuit according to the duration signal, a sawtooth signal having a plurality of values at a plurality of times within a time period of the measurement cycle, respectively, each value of the sawtooth signal corresponding to a target integrated current value for the respective time, the target integrated current value corresponding to a target average current for the measurement cycle; determining, by a comparison circuit during the time period of the measurement cycle, a reset signal indicating whether the value of the integrator output is greater than the sawtooth signal; and producing, using the reset signal, a gate signal to control the current of the SMPS circuit. ### Claim 15 (depends on 14) The method of claim 14, further comprising: producing, using an error circuit, a comparison signal having a value corresponding to a difference between a voltage value of an output of the SMPS circuit and a target output voltage value; and producing, by an oscillator circuit according to the comparison signal and a result of a division of the comparison signal by the duration signal, the sawtooth signal. ### Claim 16 (depends on 15) The method of claim 15, further comprising: de-asserting the gate signal in response to the reset signal indicating that the integrator output is greater than the sawtooth signal; setting the sawtooth signal to a value according to the comparison signal in response to an assertion of the gate signal; and decreasing a value of the sawtooth signal at a rate determined according to the result of a division of the comparison signal by the duration signal when the gate signal is asserted. ### Claim 17 (depends on 14) The method of claim 14, wherein the time period of the measurement cycle is a charging period of a device in the SMPS circuit through which the current of the SMPS circuit flows. ### Claim 18 (depends on 14) The method of claim 14, further comprising: resetting, by the integrator circuit, the integrator output to zero in response to the reset signal indicating that the integrator output is greater than the sawtooth signal. ### Claim 19 (depends on 14) The method of claim 14, further comprising: producing, by a duration determining circuit, the duration signal using a zero crossing detect signal generated according to the current of the SMPS circuit. ### Claim 20 (depends on 14) The method of claim 14, wherein the SMPS circuit is a Power Factor Correction (PFC) circuit.