Resistive memory device having a template layer
Assignee4D-S, Ltd.
InventorSeshubabu Desu
Life of this patent
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Abstract
A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.
Claims23
A memory device, comprising:
- a template layer;
- a memory layer connected to the template layer, wherein the memory layer has a variable resistance, and wherein the crystalline structure of the memory layer matches the crystalline structure of the template layer;
- and
- a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure.
A method of manufacturing a memory device, the method comprising:
- forming a template layer;
- connecting a memory layer to the template layer, wherein the memory layer has a variable resistance, and wherein the crystalline structure of the memory layer matches the crystalline structure of the template layer;
- and forming a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure.
A method of using a memory device, the memory device comprising a template layer, a memory layer connected to the template layer, the memory layer having a variable resistance, wherein the crystalline structure of the memory layer matches the crystalline structure of the template layer, and wherein the memory device further comprises a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, the method comprising:
- applying a first voltage difference across the template layer and the top electrode, whereby an electric field is generated in the memory layer, and such that a resistivity state of the memory layer is changed;
- applying a second voltage difference across the template layer and the top electrode;
- while the second voltage difference is applied, causing a first current to be conducted through the template layer, the memory layer, and the top electrode;
- and determining the resistivity state of the memory layer based on the second voltage and the first current.
Dependencies are inferred from the claim text.