# US 10,319,857 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,319,857 B2
- Document ID: US10319857B2
- Status: Granted
- Kind: B2
- Application number: 15/796,853
- Filed: 2017-10-30
- Published: 2018-03-08
- Granted: 2019-06-11
- Earliest claimed: 2015-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Fen Chen; Chui-Ya Peng; Ching Yu; Pin-Hen Lin; Yen Chuang; Yuh-Ta Fan
- Web page: https://patentgrep.com/patent/US10319857B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising silicon;
an epitaxy structure in the substrate;
an isolation structure in the substrate and having a sidewall facing the epitaxy structure;
a gate stack adjacent the epitaxy structure;
a spacer on a sidewall of the gate stack;
a silicide region over the epitaxy structure and in contact with the spacer; and
a liner in contact with the silicide region and between the substrate and the epitaxy structure, wherein the liner includes silicon denser than that in the substrate, the sidewall of the isolation structure facing the epitaxy structure has a first portion in contact with the liner and a second portion over the first portion, the second portion is free from coverage by the liner, and the epitaxy structure is spatially separated from the spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the liner defines at least one round corner.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a radius of curvature of the round corner is about 20 nm to about 60 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack is over the substrate, and the liner is between the gate stack and the epitaxy structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the epitaxy structure is arranged between the isolation structure and the gate stack.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the substrate has a doped region between the epitaxy structure and the gate stack.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the liner and the substrate are made of substantially the same material.

### Claim 8

A semiconductor device, comprising:
a substrate;
a liner in the substrate;
an isolation structure in the substrate;
an epitaxy structure over the liner and in contact with the isolation structure;
a gate stack over the substrate; and
a spacer on a sidewall of the gate stack, wherein the epitaxy structure is spatially separated from the spacer by the liner and the liner includes an outer surface and an inner surface that has less number of corners than the outer surface thereof.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the epitaxy structure has a top portion that extends from the liner and protrudes above a top surface of the substrate.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the epitaxy structure further has a bottom portion between the top portion and the substrate, and the bottom and top portions of the epitaxy structure are made from a same material.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the epitaxy structure further has a bottom portion between the top portion and the substrate, and the bottom and top portions of the epitaxy structure have a same lattice constant.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising a silicide region over the epitaxy structure and in contact with the spacer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the epitaxy structure is between the silicide region and the liner.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the outer surface and the inner surface of the liner are in contact with the substrate and the epitaxy structure, respectively.

### Claim 15

A semiconductor device, comprising:
a substrate;
an epitaxy structure in the substrate;
an isolation structure in the substrate;
a liner between the substrate and the epitaxy structure;
a gate stack over the substrate;
a spacer on a sidewall of the gate stack; and
a silicide region over the epitaxy structure and in contact with the isolation structure, the liner, and the spacer, wherein an interface between the liner and the silicide region is level with a bottom surface of the spacer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein an inner surface of the liner is smoother than an outer surface of the liner.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the liner and the substrate are made of substantially the same material.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the epitaxy structure has at least one round corner.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the epitaxy structure has facets.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the gate stack is over the substrate and adjacent to the epitaxy structure.