# US 10,319,856 B2 · Semiconductor device

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- Number: US 10,319,856 B2
- Document ID: US10319856B2
- Status: Granted
- Kind: B2
- Application number: 15/832,755
- Filed: 2017-12-05
- Published: 2018-04-05
- Granted: 2019-06-11
- Earliest claimed: 2015-11-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: En-Chiuan Liou; Yu-Cheng Tung
- Web page: https://patentgrep.com/patent/US10319856B2

## CPC

- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 62/57: the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
- H10D 62/80: characterised by the materials
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10P 14/3402: {characterised by the chemical composition}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/214: {Recoil-implantation}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
two gate structures disposed on the substrate;
an epitaxial layer disposed in the substrate between two gate structures;
a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines, and the two non-parallel slanting lines compose a V profile;
a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and the two non-parallel slanting lines compose a reverse V profile, and wherein the first dislocation does not contact a top surface of the epitaxial layer directly, and an intersection point of the at least two non-parallel slanting lines of the first dislocation is disposed in the epitaxial layer, wherein the intersection point is disposed below the top surface of the epitaxial layer; and
a contact structure directly contacts the top surface of the epitaxial layer, wherein part of the contact structure is disposed lower than a top surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the contact structure comprises silicide.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the contact structure has a bottommost surface with a V-shaped profile.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the bottommost surface of the contact structure directly contact with the second dislocation.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure is a gate structure of an n-type metal-oxide-silicon (NMOS) field-effect transistor (FET).

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the material of the epitaxial layer includes SiC, SiP, or SiCP.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising two spacers each respectively disposed on two sides of each gate structure, wherein the second dislocation contacts the spacer directly.

### Claim 8

A semiconductor device, comprising:
a substrate;
two gate structures disposed on the substrate;
an epitaxial layer disposed in the substrate between two gate structures, wherein a bottom portion of the epitaxial layer is larger than a top portion thereof;
a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines, and the two non-parallel slanting lines compose a V profile, and an intersection point of the at least two non-parallel slanting lines of the second dislocation is disposed in the epitaxial layer, wherein the intersection point is disposed below the top surface of the epitaxial layer; and
a contact structure directly contacts the top surface of the epitaxial layer, wherein part of the contact structure is disposed lower than a top surface of the substrate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the contact structure comprises silicide.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the contact structure has a bottommost surface with a V-shaped profile.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the bottommost surface of the contact structure directly contact with the second dislocation.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the gate structure is a gate structure of an n-type metal-oxide-silicon (NMOS) field-effect transistor (FET).

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the material of the epitaxial layer includes SiC, SiP, or SiCP.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, further comprising two spacers each respectively disposed on two sides of each gate structure, wherein the second dislocation contacts the spacer directly.