# US 10,319,853 B2 · Semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,853 B2
- Document ID: US10319853B2
- Status: Granted
- Kind: B2
- Application number: 15/868,389
- Filed: 2018-01-11
- Published: 2018-05-17
- Granted: 2019-06-11
- Earliest claimed: 2009-09-07
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Shuhei Mitani; Yuki Nakano; Heiji Watanabe; Takayoshi Shimura; Takuji Hosoi; Takashi Kirino
- Web page: https://patentgrep.com/patent/US10319853B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 12/031: {of IGBTs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 62/8325: {Silicon carbide}
- H10D 64/01366: {the semiconductor being silicon carbide}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/035: {using silicon carbide [SiC] technology}
- H10P 14/6304: {Formation by oxidation, e.g. oxidation of the substrate}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6316: {Formation by nitridation, e.g. nitridation of the substrate}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon carbide layer;
a gate trench formed at a surface of the silicon carbide layer;
a gate insulating film formed over the gate trench; and
a gate electrode formed over the gate insulating film,
wherein the silicon carbide layer includes a drain region, a well region formed over the drain region, and a source region formed over the well region,
wherein the gate trench is formed through the well region and to the surface of the silicon carbide layer so that a part of the gate insulating film is exposed from the gate trench at the surface of the silicon carbide layer, and
wherein, in a cross-sectional view, a width of the gate insulating film from one side of the gate trench to an opposite side of the gate trench is greater at portion of the silicon carbide layer in which the source region is formed than at a base of the gate trench.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
a thickness of the gate insulating film is not less than 1 nm.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein
the silicon carbide layer is of a first conductivity type,
the semiconductor device further comprises:
a second conductivity type well region formed at a surface layer portion of the silicon carbide layer; and
a first conductivity type source region formed at a surface layer portion of the well region,
wherein the gate electrode is opposed to a channel region of the well region where a channel is formed through the gate insulating film.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein an impurity concentration in a first region of a prescribed width adjacent to the channel region is lower than an impurity concentration in a second region other than the first region in the source region.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3, wherein
the source region and the channel region are adjacently formed in a direction along an upper surface of the silicon carbide layer, and
the gate insulating film is formed on the upper surface of the silicon carbide layer.

### Claim 6 (depends on 3)

The semiconductor device according to claim 3, wherein
the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the silicon carbide layer, and
the silicon carbide layer further includes a trench dug down from the upper surface of the source region to pass through the source region to the well region, and
the gate insulating film is formed on the inner surface of the trench.

### Claim 7 (depends on 3)

The semiconductor device according to claim 3, further comprising:
a source terminal connecting a plurality of the source regions including the source region;
a gate terminal connected to the gate electrode at the surface of the silicon carbide layer; and
a drain terminal formed on the rear side of the silicon carbide layer.

### Claim 8 (depends on 4)

The semiconductor device according to claim 4, wherein a density of the first portion is different from a density of the second portion.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the source region in a vertical direction is smaller than a width of the well region in the vertical direction.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the drain region contacts both a sidewall and a bottom wall of the gate trench.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, further comprising a contact region of a second conductivity type at the surface of the silicon carbide layer.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the contact region reaches to the well region in a vertical direction.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the source region in a vertical direction is about 0.2 μm.