# US 10,319,852 B2 · Forming eDRAM unit cell with VFET and via capacitance

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- Number: US 10,319,852 B2
- Document ID: US10319852B2
- Status: Granted
- Kind: B2
- Application number: 15/671,589
- Filed: 2017-08-08
- Published: 2018-07-26
- Granted: 2019-06-11
- Earliest claimed: 2017-01-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Huiming Bu; Xuefeng Liu; Junli Wang
- Web page: https://patentgrep.com/patent/US10319852B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/036: {the capacitor extending under the transistor}
- H10B 12/0385: {Making a connection between the transistor and the capacitor, e.g. buried strap}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/33: {the capacitor extending under the transistor}
- H10B 12/36: {the transistor being a FinFET}
- H10D 1/692: {Electrodes}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6728: {Vertical TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.

## Claims

### Claim 1

An embedded dynamic random access memory (eDRAM) device, comprising:
a FinFET (fin field effect transistor) device having a plurality of fins formed over a substrate; and
a via cap formed adjacent the FinFET device by including:
a trench capacitor extending to and directly contacting a top surface of an epitaxial layer, the epitaxial layer directly contacting a top surface of the substrate and sidewalls of each of the plurality of fins;
a conductive liner deposited within the trench capacitor;
a high-k material deposited within the trench capacitor; and
a conducting material deposited over the high-k material.

### Claim 2 (depends on 1)

The device of claim 1, wherein a high-k dielectric is formed adjacent the plurality of fins.

### Claim 3 (depends on 2)

The device of claim 2, wherein an oxide layer is deposited over the plurality of fins and a top spacer is deposited over the oxide layer.

### Claim 4 (depends on 3)

The device of claim 3, wherein a first epitaxial region is formed at one end of the plurality of fins and a second epitaxial region is formed at the other end of the plurality of fins to form source and drain regions.

### Claim 5 (depends on 4)

The device of claim 4, wherein the top and bottom spacers isolate the source and drain regions by the via cap.

### Claim 6 (depends on 1)

The device of claim 1, wherein the conductive liner is titanium/titanium nitride/cobalt (Ti/TiN/Co).

### Claim 7 (depends on 1)

The device of claim 1, wherein the conducting material is titanium/titanium nitride/tungsten (Ti/TiN/W).

### Claim 8 (depends on 1)

The device of claim 1, wherein a self-aligned contact (CA) is formed.

### Claim 9 (depends on 8)

The device of claim 8, wherein the CA contact is filled with the conducting material used to fill the high-k material.

### Claim 10

An embedded dynamic random access memory (eDRAM) device, comprising:
a FinFET (fin field effect transistor) device having plurality of fins formed over a substrate; and
a via cap formed adjacent the FinFET device by including:
a trench capacitor extending to and directly contacting a top surface of an epitaxial layer, the epitaxial layer directly contacting a top surface of the substrate and sidewalls of each of the plurality of fins;
a high-k material deposited within the trench capacitor;
a conducting material deposited over the high-k material; and
a self-aligned contact (CA) formed thereon.

### Claim 11 (depends on 10)

The device of claim 10, wherein a conductive liner is deposited within the trench capacitor before depositing the high-k material.

### Claim 12 (depends on 10)

The device of claim 10, wherein the CA contact is filled with the conducting material used to fill the high-k material.

### Claim 13 (depends on 10)

The device of claim 10, wherein the conducting material is titanium/titanium nitride/tungsten (Ti/TiN/W).

### Claim 14 (depends on 10)

The device of claim 10, wherein a first epitaxial region is formed at one end of the plurality of fins and a second epitaxial region is formed at the other end of the plurality of fins to form source and drain regions.

### Claim 15 (depends on 14)

The device of claim 14, wherein top and bottom spacers isolate the source and drain regions by the via cap.