# US 10,319,848 B2 · Vertical DMOS transistor

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- Number: US 10,319,848 B2
- Document ID: US10319848B2
- Status: Granted
- Kind: B2
- Application number: 16/017,686
- Filed: 2018-06-25
- Published: 2018-10-25
- Granted: 2019-06-11
- Earliest claimed: 2012-12-19
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Hideaki Tsuchiko
- Web page: https://patentgrep.com/patent/US10319848B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 50/642: {Chemical etching}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.

## Claims

### Claim 1

A transistor, comprising:
a semiconductor body of a first conductivity type;
a first gate electrode formed on a first portion of the semiconductor body and insulated from the semiconductor body by a gate dielectric layer, a drain region of a second conductivity type formed on a first side of the first gate electrode and a first source region of the second conductivity type formed on a second side of the first gate electrode, the second side opposite the first side;
a second gate electrode formed on a second portion of the semiconductor body and insulated from the semiconductor body by the gate dielectric layer, the drain region being formed on a first side of the second gate electrode and a second source region of the second conductivity type formed on a second side of the second gate electrode;
a trench formed in the semiconductor body and positioned in the drain region, the trench being lined with a thin dielectric layer as a sidewall dielectric layer, the trench being filled with a bottom dielectric layer at a lower portion of the trench and a conductive layer above the bottom dielectric layer, the conductive layer being electrically connected to the gate electrode, wherein the first and second portions of the semiconductor body are on opposite sides of the trench; and
a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench outside of the trench, the doped sidewall region being in electrical contact with the drain region and forming a vertical drain current path for the transistor, the drain current of the transistor flowing in the doped sidewall region in the semiconductor body outside of the trench.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the conductive layer formed in the trench is electrically connected to the first and second gate electrodes to form a trench conductive field plate for the vertical drain current path, the field plate being biased to an accumulation mode when the transistor is turned on to reduce the resistivity of the vertical drain current path.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the thin dielectric layer comprises a thin oxide layer and the conductive layer in the trench comprises a polysilicon layer.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length does not equal the second length.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length being the same as the second length.

### Claim 6 (depends on 1)

The transistor of claim 1, wherein the semiconductor body comprises:
a substrate of the first conductivity type;
a buried layer of the second conductivity type formed on the substrate; and
an epitaxial layer formed on the substrate and a well region of the first conductivity type formed in the epitaxial layer,
wherein the first and second portions of the semiconductor body and the trench are formed in the well region and the trench reaches at least the buried layer and the drain current of the transistor flows through the doped sidewall region to the buried layer.

### Claim 7 (depends on 6)

The transistor of claim 6, further comprising:
a second trench formed in the semiconductor body remote from the trench and reaching at least the buried layer, the second trench being lined with a second sidewall dielectric layer and filled with a second conductive layer; and
a trench bottom doped region of the second conductivity type being formed in the semiconductor body beneath the second trench,
wherein the second conductive layer of the second trench is in electrical contact with the trench bottom doped region and the buried layer, the second conductive layer forming a trench drain electrode conducting the drain current of the transistor.

### Claim 8 (depends on 7)

The transistor of claim 7, wherein the second conductive layer comprises one of aluminum or tungsten.

### Claim 9 (depends on 1)

The transistor of claim 1, wherein the transistor comprises a double-diffused MOS transistor with a lateral channel under the first and second gate electrodes and the drain current flows from the drain region to the vertical drain current path in the doped sidewall region along the sidewall of the trench.

### Claim 10 (depends on 1)

The transistor of claim 1, wherein the drain region is more heavily doped than the doped sidewall region.

### Claim 11 (depends on 1)

The transistor of claim 1, wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity.

### Claim 12

A transistor, comprising:
a semiconductor body of a first conductivity type;
a first gate electrode formed on a first portion of the semiconductor body and insulated from the semiconductor body by a gate dielectric layer, a drain region of a second conductivity type formed on a first side of the first gate electrode and a first source region of the second conductivity type formed on a second side of the first gate electrode, the second side opposite the first side;
a second gate electrode formed on a second portion of the semiconductor body and insulated from the semiconductor body by the gate dielectric layer, the drain region being formed on a first side of the second gate electrode and a second source region of the second conductivity type formed on a second side of the second gate electrode;
a trench formed in the semiconductor body and positioned in the drain region, the trench being lined with a thin dielectric layer as a sidewall dielectric layer;
a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench outside of the trench, the doped sidewall region being in electrical contact with the drain region and forming a vertical drain current path for the transistor, the drain current of the transistor flowing in the doped sidewall region in the semiconductor body outside of the trench;
a trench bottom doped region of the second conductivity type formed in the semiconductor body beneath the trench and in electrical contact with the doped sidewall region formed in the semiconductor body along the sidewall of the trench,
wherein the trench is filled at an outer perimeter with a bottom dielectric layer at a lower portion of the trench and a first conductive layer above the bottom dielectric layer, and the remaining portion of the trench is filled with a second conductive layer in electrical contact with the trench bottom doped region, the second conductive layer being electrically insulated from the first conductive layer by a dielectric layer, the second conductive layer forming a trench drain electrode, the drain current of the transistor flowing in the vertical drain current path is directed to the trench bottom doped region and to the trench drain electrode.

### Claim 13 (depends on 12)

The transistor of claim 12, wherein the first conductive layer formed in the trench is electrically connected to the first and second gate electrodes or to the first and second source regions.

### Claim 14 (depends on 12)

The transistor of claim 12, wherein the first conductive layer formed in the trench is electrically connected to the first and second gate electrodes to form a trench conductive field plate for the vertical drain current path, the field plate being biased to an accumulation mode when the transistor is turned on to reduce the resistivity of the vertical drain current path.

### Claim 15 (depends on 12)

The transistor of claim 12, wherein the thin dielectric layer comprises a thin oxide layer, the first conductive layer comprises a polysilicon layer and the second conductive layer comprises one of aluminum or tungsten.

### Claim 16 (depends on 12)

The transistor of claim 12, wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length does not equal the second length.

### Claim 17 (depends on 12)

The transistor of claim 12, wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length being the same as the second length.

### Claim 18 (depends on 12)

The transistor of claim 12, wherein the semiconductor body comprises:
a substrate of the first conductivity type; and
an epitaxial layer formed on the substrate and a well region of the first conductivity type formed in the epitaxial layer,
wherein the first and second portions of the semiconductor body and the trench are formed in the well region.

### Claim 19 (depends on 12)

The transistor of claim 12, wherein the transistor comprises a double-diffused MOS transistor with a lateral channel under the gate electrode and a vertical drain current path in the doped sidewall region along the sidewall of the trench.

### Claim 20 (depends on 12)

The transistor of claim 12, wherein the drain region is more heavily doped than the doped sidewall region.