# US 10,319,846 B1 · Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness

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- Number: US 10,319,846 B1
- Document ID: US10319846B1
- Status: Granted
- Kind: B1
- Application number: 15/975,364
- Filed: 2018-05-09
- Granted: 2019-06-11
- Earliest claimed: 2018-05-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Takashi Ando; ChoongHyun Lee; Jingyun Zhang; Pouya Hashemi
- Web page: https://patentgrep.com/patent/US10319846B1

## CPC

- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a plurality of nanosheet channels disposed over an isolation layer disposed over a substrate, the plurality of nanosheet channels comprising a first set of two or more nanosheet channels for a first negative-channel field-effect transistor (NFET), a second set of two or more nanosheet channels for a second NFET, a third set of two or more nanosheet channels for a first positive-channel field-effect transistor (PFET) and a fourth set of two or more nanosheet channels for a second PFET;
forming interfacial layers surrounding each of the nanosheet channels; forming dielectric layers surrounding each of the nanosheet channels; forming a first capping metal layer over the first set of two or more nanosheet channels for the first NFET and the third set of two or more nanosheet channels for the first PFET;
forming a second capping metal layer different than the first capping metal layer over the second set of two or more nanosheet channels for the second NFET and the fourth set of two or more nanosheet channels for the second PFET; performing an anneal to selectively thin the interfacial layers surrounding the second set of two or more nanosheet channels for the second NFET and the fourth set of two or more nanosheet channels for the second PFET; and
wherein, subsequent to the anneal: the interfacial layers surrounding the first set of two or more nanosheet channels for the first NFET and the interfacial layers surrounding the third set of two or more nanosheet channels for the first PFET have a first thickness; the interfacial layers surrounding the second set of two or more nanosheet channels for the second NFET and the interfacial layers surrounding the fourth set of two or more nanosheet channels for the second PFET have a second thickness smaller than the first thickness; the first NFET has a higher threshold voltage than the second NFET; and the first PFET has a lower threshold voltage than the second PFET.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first thickness is greater than five angstroms (Å) and the second thickness is less than five Å.

### Claim 3 (depends on 1)

The method of claim 1, wherein the anneal comprises a spike anneal at a first temperature followed by a laser spike anneal at a second temperature greater than the first temperature.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first temperature is greater than 900 degrees Celsius (° C.) and the second temperature is greater than 1100° C.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first capping metal comprises a multilayer comprising an aluminum-containing alloy layer disposed between nanosheet channels in the first set of two or more nanosheet channels for the first NFET and disposed between nanosheet channels in the third set of two or more nanosheet channels for the first PFET.

### Claim 6 (depends on 5)

The method of claim 5, wherein the nanosheet channels comprise silicon (Si) and the interfacial layers comprise silicon dioxide (SiO2).

### Claim 7 (depends on 5)

The method of claim 5, wherein the aluminum-containing alloy layer comprises titanium aluminum carbide (TiAlC).

### Claim 8 (depends on 5)

The method of claim 5, wherein the multilayer comprises:
a first titanium nitride (TiN) layer disposed surrounding the first set of two or more nanosheet channels for the first NFET and the third set of two or more nanosheet channels for the first PFET;
the aluminum-containing alloy layer disposed surrounding the first TiN layer and pinching off spaces between the first set of two or more nanosheet channels for the first NFET and the third set of two or more nanosheet channels for the first PFET; and
a second TiN layer surrounding the aluminum-containing alloy layer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the second capping metal comprises a third TiN layer surrounding and pinching off spaces between the second set of two or more nanosheet channels for the second NFET and the fourth set of two or more nanosheet channel for the second PFET.

### Claim 10 (depends on 8)

The method of claim 8, further comprising forming an amorphous silicon (a-Si) layer over the first capping metal and the second capping metal.