# US 10,319,844 B2 · Semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,844 B2
- Document ID: US10319844B2
- Status: Granted
- Kind: B2
- Application number: 15/446,642
- Filed: 2017-03-01
- Published: 2018-03-22
- Granted: 2019-06-11
- Earliest claimed: 2016-09-16
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Mitsuhiko Kitagawa
- Web page: https://patentgrep.com/patent/US10319844B2

## CPC

- H10D 12/441: {Vertical IGBTs}
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/135: {Non-interconnected multi-emitter structures}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/141: {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs}
- H10D 62/145: {Emitter regions of IGBTs}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/141: {VDMOS having built-in components}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to the fifth semiconductor region.

## Claims

### Claim 1

A semiconductor device comprising:
a first electrode;
a first semiconductor region of a first conductivity type that is disposed on the first electrode and is electrically connected to the first electrode;
a second semiconductor region of the first conductivity type that is disposed on the first semiconductor region and has a carrier concentration of the first conductivity type lower than a carrier concentration of the first semiconductor region;
a third semiconductor region of a second conductivity type that is disposed on the second semiconductor region;
a fourth semiconductor region of the first conductivity type that is disposed on the third semiconductor region;
a second electrode that is disposed on the fourth semiconductor region and is electrically connected to the fourth semiconductor region;
a fifth semiconductor region of the second conductivity type that is disposed on the second semiconductor region and is separated from the third semiconductor region in a first direction;
a third electrode that is disposed on the fifth semiconductor region, is separated from the second electrode, and is electrically connected to the fifth semiconductor region;
a first gate insulating layer;
a first gate electrode that is disposed on the second semiconductor region, faces the third semiconductor region via the first gate insulating layer in the first direction, and is positioned between the third semiconductor region and the fifth semiconductor region;
a sixth semiconductor region of the first conductivity type that is disposed between the second semiconductor region and the third semiconductor region and has a carrier concentration of the first conductivity type higher than the carrier concentration of the second semiconductor region; and
a seventh semiconductor region of the first conductivity type that is disposed between the second semiconductor region and the fifth semiconductor region and has a carrier concentration of the first conductivity type higher than the carrier concentration of the second semiconductor region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second gate insulating layer; and
a second gate electrode that is disposed between the fifth semiconductor region and the first gate electrode and faces the fifth semiconductor region via the second gate insulating layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a voltage different from a voltage of the second electrode is applied to the third electrode.

### Claim 4

A semiconductor device comprising:
a first electrode;
a first semiconductor region of a first conductivity type that is disposed on the first electrode and is electrically connected to the first electrode;
a second semiconductor region of the first conductivity type that is disposed on the first semiconductor region and has a carrier concentration of the first conductivity type lower than a carrier concentration of the first semiconductor region;
a third semiconductor region of a second conductivity type that is disposed on the second semiconductor region;
a fourth semiconductor region of the first conductivity type that is disposed on the third semiconductor region;
a second electrode that is disposed on the fourth semiconductor region and is electrically connected to the fourth semiconductor region;
a fifth semiconductor region of the second conductivity type that is disposed on the second semiconductor region and is separated from the third semiconductor region in a first direction;
a third electrode that is disposed on the fifth semiconductor region, is separated from the second electrode, and is electrically connected to the fifth semiconductor region;
a first gate insulating layer;
a first gate electrode that is disposed on the second semiconductor region, faces the third semiconductor region via the first gate insulating layer in the first direction, and is positioned between the third semiconductor region and the fifth semiconductor region;
a first insulating part that is disposed on the second semiconductor region, is positioned between the third semiconductor region and the fifth semiconductor region in the first direction, and includes the first gate insulating layer;
a second insulating part that is disposed on the second semiconductor region, the third semiconductor region being positioned between the first insulating part and the second insulating part in the first direction; and
a third insulating part that is disposed on the second semiconductor region, the fifth semiconductor region being positioned between the first insulating part and the third insulating part in the first direction,
wherein a distance between at least a part of the first insulating part and at least a part of the second insulating part in the first direction is 1.0 μm or less, and
a distance between at least a part of the first insulating part and at least a part of the third insulating part in the first direction is 1.0 μm or less.

### Claim 5

A semiconductor device comprising:
first electrode;
a first semiconductor region of a first conductivity type that is disposed on the first electrode and is electrically connected to the first electrode;
a second semiconductor region of the first conductivity type that is disposed on the first semiconductor region and has a carrier concentration of the first conductivity type lower than a carrier concentration of the first semiconductor region;
a third semiconductor region of a second conductivity type that is disposed on the second semiconductor region;
a fourth semiconductor region of the first conductivity type that is disposed on the third semiconductor region;
a second electrode that is disposed on the fourth semiconductor region and is electrically connected to the fourth semiconductor region;
a fifth semiconductor region of the second conductivity type that is disposed on the second semiconductor region and is separated from the third semiconductor region in a first direction;
a third electrode that is disposed on the fifth semiconductor region, is separated from the second electrode, and is electrically connected to the fifth semiconductor region;
a first gate insulating layer;
a first gate electrode that is disposed on the second semiconductor region, faces the third semiconductor region via the first gate insulating layer in the first direction, and is positioned between the third semiconductor region and the fifth semiconductor region;
second insulating part that is disposed on the second semiconductor region, the third semiconductor region being positioned between the first insulating part and the second insulating part in the first direction; and
a third insulating part that is disposed on the second semiconductor region, the fifth semiconductor region being positioned between the first insulating part and the third insulating part in the first direction,
wherein a distance between at least a part of the first insulating part and at least a part of the second insulating part in the first direction is 1.0 μm or less, and
a distance between at least a part of the first insulating part and at least a part of the third insulating part in the first direction is 1.0 μm or less,
wherein a length of the first insulating part in the first direction is two times the distance between the part of the first insulating part and the part of the second insulating part or more and is twice the distance between the part of the first insulating part and the part of the third insulating part or more.