# US 10,319,839 B2 · Semiconductor structure and fabrication method thereof

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- Number: US 10,319,839 B2
- Document ID: US10319839B2
- Status: Granted
- Kind: B2
- Application number: 15/473,703
- Filed: 2017-03-30
- Published: 2017-11-30
- Granted: 2019-06-11
- Earliest claimed: 2016-05-27
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Zhong Shan Hong; Ke Lu Hua; Jin Peng
- Web page: https://patentgrep.com/patent/US10319839B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/60: Impurity distributions or concentrations
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6213: {having rounded corners}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a base substrate;
forming a sacrificial material layer on the base substrate;
forming a mask layer on the sacrificial material layer;
forming the sacrificial layer and the fins using the mask layer as a mask to etch the sacrificial material layer and the base substrate;
removing the mask layer, wherein each fin includes a first sidewall and a second sidewall opposing each other;
removing a thickness portion of the sacrificial layer;
performing a first ion implantation process on the first sidewall and a top of the fin; and
performing a second ion implantation process on the second sidewall and the top of the fin.

### Claim 2

A method for fabricating a semiconductor structure, comprising:
providing a base substrate;
forming a sacrificial material layer on the base substrate;
forming a mask layer on the sacrificial material layer;
forming the sacrificial layer and the fins using the mask layer as a mask to etch the sacrificial material layer and the base substrate;
removing the mask layer, wherein each fin includes a first sidewall and a second sidewall opposing each other;
forming a liner layer covering the first sidewall and the second sidewall of each fin, wherein a thickness of the sacrificial layer is larger than a thickness of the liner layer;
performing a first ion implantation process on the first sidewall and a top of the fin; and
performing a second ion implantation process on the second sidewall and the top of the fin.

### Claim 3 (depends on 2)

The method according to claim 2, wherein forming the liner layer on the first sidewall and the second sidewall includes one of:
a deposition process and a furnace tube process.

### Claim 4 (depends on 2)

The method according to claim 2, wherein:
the thickness of the liner layer is smaller than the thickness of the sacrificial layer by approximately 1 nm-2 nm.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the first ion implantation process and the second ion implantation process include:
using a lateral ion implantation process to perform the first ion implantation process; and
using a lateral ion implantation process to perform the second ion implantation process.

### Claim 6 (depends on 1)

The method according to claim 1, wherein each of the first ion implantation process and the second ion implantation process includes:
an implantation angle in a range of approximately 30°-80°.

### Claim 7 (depends on 1)

The method according to claim 1, wherein forming the mask layer includes:
a multiple patterning process including a self-aligned double patterned (SaDP) process, a self-aligned triple patterned (SaTP) process, or a self-aligned double patterned (SaDDP) process.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
the mask layer includes at least one silicon nitride layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherein each of the sacrificial material layer and the mask layer is formed by one of:
a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and a furnace tube process.

### Claim 10 (depends on 1)

The method according to claim 1, after forming the substrate and before forming the sacrificial layer, further including:
filling a space between adjacent fins with an isolation layer.

### Claim 11 (depends on 1)

The method according to claim 1, wherein, during the first ion implantation process and the second ion implantation process:
implantation depths of the first ion implantation process and the second ion implantation process are smaller than 10 nm.

### Claim 12 (depends on 1)

The method according to claim 1, after performing the first ion implantation process and the second ion implantation process, further including:
removing the sacrificial layer to expose the top of the one or more fins.

### Claim 13 (depends on 12)

The method according to claim 12, wherein removing the sacrificial layer includes:
a thinning process.

### Claim 14 (depends on 12)

The method according to claim 12, after removing the sacrificial layer, further including:
performing a corner rounding process on the one or more fins.

### Claim 15 (depends on 14)

The method according to claim 14, wherein performing the corner rounding process includes:
an annealing treatment using a process gas including helium, hydrogen, or a combination thereof and a process temperature in a range of approximately 600° C.-900° C.