# US 10,319,835 B2 · Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

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- Number: US 10,319,835 B2
- Document ID: US10319835B2
- Status: Granted
- Kind: B2
- Application number: 15/813,528
- Filed: 2017-11-15
- Published: 2018-11-22
- Granted: 2019-06-11
- Earliest claimed: 2017-05-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Su Chen Fan; Zuoguang Liu; Heng Wu; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US10319835B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/01: Manufacture or treatment
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/0698: {Local interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
forming a semiconductor fin on a doped region of a substrate;
recessing a surface of the doped region, the recessed surface comprising a first portion adjacent to a first sidewall of the semiconductor fin, a second portion adjacent to a second sidewall of the semiconductor fin, and a third portion adjacent to a third sidewall of the semiconductor fin; and
forming a conductive layer on the first portion, the second portion, and the third portion of the recessed surface of the doped region;
wherein a conductivity of the conductive layer is higher than a conductivity of the doped region.

### Claim 2 (depends on 1)

The method of claim 1 further comprising forming a conductive gate over a channel region of the semiconductor fin.

### Claim 3 (depends on 2)

The method of claim 2 further comprising forming a bottom spacer between the doped region and the conductive gate.

### Claim 4 (depends on 3)

The method of claim 3 further comprising forming a top spacer over the conductive gate and the bottom spacer.

### Claim 5 (depends on 1)

The method of claim 1 further comprising forming a conductive contact on a surface of the semiconductor fin.

### Claim 6 (depends on 1)

The method of claim 1 further comprising forming a conductive contact on a surface of the conductive layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the conductive layer wraps around three sides of the semiconductor fin.

### Claim 8 (depends on 1)

The method of claim 1, wherein the conductive layer comprises a metal.

### Claim 9 (depends on 1)

The method of claim 1, wherein the conductive layer comprises titanium.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming the conductive layer comprises conformally depositing a conductive material over the recessed surface of the doped region and over sidewalls of the conductive gate.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the conductive layer further comprises removing the portions of the conductive layer deposited on sidewalls of the conductive gate.

### Claim 12 (depends on 1)

The method of claim 1, wherein the recessed surface of the doped region is recessed about 10 to about 15 nm.

### Claim 13

A method for forming a semiconductor device, the method comprising:
forming a semiconductor fin on a doped region of a substrate;
forming a conductive gate over a channel region of the semiconductor fin;
recessing a portion of the doped region adjacent to the semiconductor fin;
forming a conductive rail on the recessed portion of the doped region;
forming a dielectric layer between the conductive rail and the conductive gate;
forming a first conductive contact on a surface of the conductive rail; and
forming a second conductive contact on a surface of the semiconductor fin;
wherein a conductivity of the conductive rail is higher than a conductivity of the doped region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the conductive rail wraps around three sides of the semiconductor fin.

### Claim 15 (depends on 13)

The method of claim 13, wherein the conductive rail comprises a metal.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the conductive rail comprises depositing the metal over the recessed portion of the doped region and over sidewalls of the conductive gate.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the conductive rail further comprises removing the portions of the conductive rail deposited on sidewalls of the conductive gate.

### Claim 18 (depends on 13)

The method of claim 13, wherein the conductive rail comprises a thickness of about 7 to about 12 nm.

### Claim 19

A method of operating a semiconductor device, the method comprising:
providing a semiconductor device comprising:
a semiconductor fin on a bottom doped region of a substrate;
a conductive gate formed over a channel region of the semiconductor fin;
a top doped region on a surface of the semiconductor fin;
a top source/drain (S/D) contact on a surface of the top doped region;
a conductive rail on a recessed portion of the doped region; and
a bottom S/D contact on a surface of the conductive rail; and
passing a current from the top S/D contact to the bottom S/D contact through a portion of the conductive rail.

### Claim 20 (depends on 19)

The method of claim 19 further comprising a first conductive path passing through a first portion of the semiconductor fin and a second conductive path passing through a second portion of the semiconductor fin.