# US 10,319,834 B2 · Poly finger fabrication for HCI degradation improvement of ultra-low-Ron EDNMOS

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,834 B2
- Document ID: US10319834B2
- Status: Granted
- Kind: B2
- Application number: 15/656,816
- Filed: 2017-07-21
- Published: 2019-01-24
- Granted: 2019-06-11
- Earliest claimed: 2017-07-21
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Lin Wei; Upinder Singh; Raj Verma Purakh
- Web page: https://patentgrep.com/patent/US10319834B2

## CPC

- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/111: {Field plates}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10P 14/40: of conductive or resistive materials
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.

## Claims

### Claim 1

A method comprising:
forming a polysilicon layer upon a gate oxide (GOX) layer over a substrate;
forming a first gate and plurality of fingers and a second gate and plurality of fingers laterally separated through the polysilicon layer down the GOX layer by:
forming a photoresist layer over the polysilicon layer;
patterning a first, second, and third pair of openings in the photoresist layer, the pairs and the openings being laterally separated and wherein each of the first pair of openings is over the first and second p-well, respectively, and the second pair of openings is over the n-sub;
patterning a single opening between and laterally separated from each opening of the third pair;
etching the polysilicon layer through the pairs and the single opening down to the GOX layer; and
stripping the photoresist layer;
forming an oxide layer over the GOX layer and along sidewalls of the first and second gates and plurality of fingers;
forming a nitride layer over the oxide layer;
removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form a nitride spacer over and adjacent to a portion of the oxide layer on opposite sides of each gate and plurality of fingers; and
forming source/drain (S/D) regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer,
wherein the substrate comprises an N-type substrate (n-sub) having a first and a second P-type well (p-well) laterally separated.

### Claim 2 (depends on 1)

The method according to claim 1, comprising forming the GOX layer to a thickness of 40 angstrom (Å) to 80 Å.

### Claim 3 (depends on 1)

The method according to claim 1, comprising patterning each opening of the second and third pairs with a lateral width of 30 nanometer (nm) to 40 nm.

### Claim 4 (depends on 1)

The method according to claim 1, wherein openings of the second and third pair and a distance between an opening of the third pair and the single opening comprise a lateral width of 30 nm to 40 nm.

### Claim 5 (depends on 1)

The method according to claim 1, comprising forming the oxide layer by:
forming an oxidation layer to a thickness of 10 Å to 30 Å;
forming a first low temperature oxide (LTO) layer to a thickness of 40 Å to 60 Å over the oxidation layer; and
forming a second LTO layer to a thickness of 40 Å to 60 Å over the first LTO layer.

### Claim 6 (depends on 1)

The method according to claim 1, comprising forming the nitride layer to a thickness of 300 Å to 400 Å.

### Claim 7 (depends on 1)

The method according to claim 1, comprising removing the portions of the nitride and oxide layers by:
reactive-ion etching (RIE).

### Claim 8

A method comprising:
forming a first and a second P-type well (p-well) laterally separated in a N-type substrate (n-sub);
forming a gate oxide (GOX) layer to a thickness of 40 angstrom (Å) to 80 Å over the n-sub;
forming a polysilicon layer over the GOX layer;
forming a first gate and plurality of fingers and a second gate and plurality of fingers laterally separated through the polysilicon layer down the GOX layer, the first and second gates formed across a portion of the first and second p-wells, respectively, and a portion the n-sub;
forming an oxidation layer to a thickness of 10 Å to 30 Å over the GOX layer and along sidewalls of the first and second gates and fingers;
forming a first and a second low temperature oxide (LTO) layer to a thickness of 40 Å to 60 Å over the oxidation layer;
forming a nitride layer to a thickness of 300 Å to 400 Å over the second LTO layer;
removing portions of the nitride, first and second LTO, and oxidation layers down to the polysilicon and GOX layers to form a nitride spacer over and adjacent to a portion of the second LTO layer on opposite sides of each gate and plurality of fingers; and
forming a source/drain (S/D) region in each p-well and the n-sub, each S/D region adjacent to a nitride spacer.

### Claim 9 (depends on 8)

The method according to claim 8, comprising forming the first and second gates and plurality of fingers by:
forming a photoresist layer over the polysilicon layer;
patterning a first, second, and third pair of openings in the photoresist layer, the pairs and the openings being laterally separated;
patterning a single opening between and laterally separated from each opening of the third pair;
etching the polysilicon layer through the pairs and the single opening down to the GOX layer; and
stripping the photoresist layer.

### Claim 10 (depends on 8)

The method according to claim 8, comprising patterning each opening of the second and third pairs and a distance between the openings with a lateral width of 30 nanometer (nm) to 40 nm.

### Claim 11 (depends on 8)

The method according to claim 8, comprising removing the portions of the nitride, first and second LTO, and oxidation layers by:
reactive-ion etching (RIE).