# US 10,319,832 B2 · FinFET device and method of forming same

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- Number: US 10,319,832 B2
- Document ID: US10319832B2
- Status: Granted
- Kind: B2
- Application number: 15/726,074
- Filed: 2017-10-05
- Published: 2018-11-01
- Granted: 2019-06-11
- Earliest claimed: 2017-04-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chung-Ting Li; Bi-Fen Wu; Jen-Hsiang Lu; Chih-Hao Chang
- Web page: https://patentgrep.com/patent/US10319832B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/0133: {at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

## Claims

### Claim 1

A method comprising:
forming a fin extending above an isolation region;
forming a sacrificial gate stack over the fin, the sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall;
forming a first spacer on the first sidewall of the sacrificial gate stack;
forming a second spacer on the second sidewall of the sacrificial gate stack, wherein forming the first spacer and forming the second spacer comprises:
forming a first spacer layer over a top surface and along the first sidewall and the second sidewall of the sacrificial gate stack;
forming a second spacer layer over the first spacer layer; and
removing lateral portions of the second spacer layer, remaining portions of the second spacer layer forming the first spacer and the second spacer;
forming a patterned mask layer having an opening therein over the sacrificial gate stack, the first spacer and the second spacer, the patterned mask layer extending along a top surface and a sidewall of the first spacer, the second spacer being exposed through the opening in the patterned mask layer;
patterning the fin using the patterned mask layer, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin; and
epitaxially growing a source/drain region in the recess.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first spacer layer and the second spacer layer comprise different materials.

### Claim 3 (depends on 1)

The method of claim 1, further comprising replacing the sacrificial gate stack with a replacement gate stack.

### Claim 4 (depends on 3)

The method of claim 3, wherein the replacement gate stack is an active gate stack.

### Claim 5 (depends on 3)

The method of claim 3, wherein the replacement gate stack is a dummy gate stack.

### Claim 6 (depends on 1)

The method of claim 1, wherein the source/drain region and the fin comprise different semiconductor materials.

### Claim 7 (depends on 1)

The method of claim 1, wherein a sidewall of the first spacer and a top surface of the first spacer layer form an angle between about 90 degrees and about 120 degrees.

### Claim 8

A method comprising:
patterning a substrate to form trenches, the substrate comprising a first semiconductor material;
filling trenches with a dielectric material to form isolation regions;
etching the isolation regions to expose fins;
forming a sacrificial gate stack along sidewalls and over top surfaces of the fins;
depositing a first spacer layer along a sidewall and over a top surface of the sacrificial gate stack and over the top surfaces of the fins;
depositing a second spacer layer over the first spacer layer;
etching the second spacer layer to remove lateral portions of the second spacer layer, remaining portions of the second spacer layer forming gate spacers;
forming a patterned mask over the sacrificial gate stack and the gate spacers, the patterned mask extending over a portion of the first spacer layer disposed over the top surfaces of the fins and not protected by the gate spacers;
etching the first spacer layer and the fins using the patterned mask, the sacrificial gate stack, and the gate spacers as a combined mask to form first recesses in the fins; and
filling the first recesses with a second semiconductor material to form source/drain regions in the first recesses.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first spacer layer and the second spacer layer comprise different materials.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first semiconductor material is different from the second semiconductor material.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
forming a dielectric layer over the source/drain regions and along the sidewalls of the sacrificial gate stack;
removing the sacrificial gate stack form a second recess in the dielectric layer; and
forming a replacement gate stack in the second recess.

### Claim 12 (depends on 11)

The method of claim 11, wherein the replacement gate stack is an active gate stack.

### Claim 13 (depends on 11)

The method of claim 11, wherein the replacement gate stack is a dummy gate stack.

### Claim 14 (depends on 11)

The method of claim 11, further comprising merging the source/drain regions to form a common source/drain region for the fins.

### Claim 15

A method comprising:
forming an isolation region over a substrate;
recessing the isolation region to expose a fin;
forming a first sacrificial gate stack over the fin, the first sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall;
forming a second sacrificial gate stack over the fin, the second sacrificial gate stack having a third sidewall and a fourth sidewall opposite the third sidewall;
forming a first spacer on the first sidewall of the first sacrificial gate stack;
forming a second spacer on the second sidewall of the first sacrificial gate stack;
forming a third spacer on the third sidewall of the second sacrificial gate stack;
forming a fourth spacer on the fourth sidewall of the second sacrificial gate stack;
forming a patterned mask layer over the first sacrificial gate stack and the second sacrificial gate stack, the patterned mask layer coving the first spacer, the second spacer and the third spacer, the patterned mask layer exposing the fourth spacer;
patterning the fin using the patterned mask layer, the first sacrificial gate stack, the second sacrificial gate stack, the first spacer, the second spacer, the third spacer and the fourth spacer as a combined mask to form a first recess and a second recess in the fin, the first recess being interposed between the first sacrificial gate stack and the second sacrificial gate stack, the second sacrificial gate stack being interposed between the first recess and the second recess;
epitaxially growing a first source/drain region in the first recess; and
epitaxially growing a second source/drain region in the second recess.

### Claim 16 (depends on 15)

The method of claim 15, further comprising replacing the first sacrificial gate stack with a dummy replacement gate stack.

### Claim 17 (depends on 15)

The method of claim 15, further comprising replacing the second sacrificial gate stack with an active replacement gate stack.

### Claim 18 (depends on 15)

The method of claim 15, wherein a width of the first source/drain region is greater than a width of the second source/drain region.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first source/drain region is spaced apart form the second sacrificial gate stack by a first distance, and wherein the second source/drain region is spaced apart form the second sacrificial gate stack by a second distance different from the first distance.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first distance is greater than the second distance.