# US 10,319,831 B2 · Semiconductor device with a gate electrode positioned in a semiconductor substrate

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- Number: US 10,319,831 B2
- Document ID: US10319831B2
- Status: Granted
- Kind: B2
- Application number: 15/300,848
- Filed: 2015-02-25
- Published: 2017-02-02
- Granted: 2019-06-11
- Earliest claimed: 2014-04-25
- Assignees: Toyota Jidosha Kabushiki Kaisha
- Applicants: Toyota Jidosha Kabushiki Kaisha
- Inventors: Toru Onishi; Shuhei Oki; Tomoharu Ikeda; Rahman Md. Tasbir
- Web page: https://patentgrep.com/patent/US10319831B2

## CPC

- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/00: Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a trench provided in a front surface of the semiconductor substrate;
a gate insulating film covering an inner surface of the trench; and
a gate electrode provided on an inner side of the gate insulating film, the gate electrode including a first layer and a second layer,
wherein
the first layer includes an outer portion of a front surface of the gate electrode,
the second layer includes a middle portion of the front surface,
the front surface of the gate electrode is provided at a position deeper than the front surface of the semiconductor substrate, and the middle portion of the front surface, which is located at a center in a width direction of the trench, is provided at a position shallower than the outer portion of the front surface, which is in contact with the gate insulating film,
the middle portion and the outer portion form a single, continuous surface, of the front surface, and
the outer portion is provided at a depth within 400 nm from the front surface of the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device as in claim 1, further comprising:
a front surface semiconductor region of a first conductivity type exposed on the front surface of the semiconductor substrate;
a top body region of a second conductivity type provided at a position deeper than the front surface semiconductor region;
a barrier region of the first conductivity type provided at a position deeper than the top body region; and
a drift region of the first conductivity type having a lower first conductivity type impurity density than the barrier region, and provided at a position deeper than the barrier region,
wherein the trench penetrates the front surface semiconductor region, the top body region, and the barrier region, and
a lower end of the trench projects into the drift region.

### Claim 3 (depends on 2)

The semiconductor device as in claim 2, further comprising:
a bottom body region provided at a position deeper than the barrier region and shallower than the drift region,
wherein the trench further penetrates the bottom body region.

### Claim 4 (depends on 1)

The semiconductor device as in claim 1, wherein the first layer is provided with a phosphorus density higher than that of the second layer prior to a heat treatment of the gate electrode, such that the middle portion is more resistant to etching than the outer portion during formation of the front surface prior to the heat treatment of the gate electrode.

### Claim 5 (depends on 1)

The semiconductor device as in claim 1, wherein the middle portion is positioned at a depth between the depth of the outer portion and the front surface of the semiconductor substrate.