# US 10,319,824 B2 · Semiconductor device includes a substrate having a bandgap wider than that of silicon and method of manufacturing semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,824 B2
- Document ID: US10319824B2
- Status: Granted
- Kind: B2
- Application number: 15/716,919
- Filed: 2017-09-27
- Published: 2018-04-05
- Granted: 2019-06-11
- Earliest claimed: 2016-10-05
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Makoto Utsumi; Akimasa Kinoshita; Yasuhiko Oonishi
- Web page: https://patentgrep.com/patent/US10319824B2

## CPC

- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 12/031: {of IGBTs}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n−-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate containing a wide bandgap semiconductor material having a bandgap wider than that of silicon;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and containing the wide bandgap semiconductor material;
a second semiconductor layer of a second conductivity type provided on a surface on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer facing the semiconductor substrate, the second semiconductor layer containing the wide bandgap semiconductor material;
a first groove penetrating both surfaces of the second semiconductor layer in a thickness direction and reaching the first semiconductor layer wherein the first groove extends to the surface of the first semiconductor layer on the first side thereof;
a third semiconductor layer of the second conductivity type provided on a surface on a first side of the second semiconductor layer opposite a second side of the second semiconductor layer facing the first semiconductor layer, the third semiconductor layer lining the first groove, an impurity concentration of the third semiconductor layer lower than that of the second semiconductor layer, the third semiconductor layer containing the wide bandgap semiconductor material;
a first semiconductor region of the first conductivity type selectively provided in the third semiconductor layer;
a trench penetrating, in the thickness direction, the third semiconductor layer in the first groove and the first semiconductor region to reach the first semiconductor layer, a width of the trench narrower than that of the first groove;
a gate insulating film provided along an inner wall of the trench;
a gate electrode provided on the gate insulating film in the trench;
a first electrode electrically connected to the first semiconductor region and the third semiconductor layer; and
a second electrode electrically connected to a rear surface of the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the second semiconductor layer and the gate insulating film are separated by the third semiconductor layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, comprising
a second groove provided at a predetermined depth from the surface on the first side of the first semiconductor layer in the thickness direction, a width of the second groove wider than that of the first groove, wherein
the second semiconductor layer lines a side of the second groove, and
the first groove penetrates the second semiconductor layer in the second groove, in the thickness direction, from the surface on the first side of the second semiconductor layer and reaches the first semiconductor layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, comprising
a second semiconductor region of the second conductivity type provided in the first semiconductor layer separately from the second semiconductor layer and the third semiconductor layer, the second semiconductor region covering at least a portion of a bottom of the trench, an impurity concentration of the second semiconductor region higher than that of the third semiconductor layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
the second semiconductor layer is an epitaxial layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
the third semiconductor layer is an epitaxial layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the wide bandgap semiconductor material is silicon carbide.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
depositing a first epitaxial layer of a first conductivity type on a front surface of a semiconductor substrate containing a semiconductor material having a bandgap wider than that of silicon;
depositing a second epitaxial layer of a second conductivity type on the first epitaxial layer;
forming a first groove penetrating both surfaces of the second epitaxial layer in a thickness direction and reaching the first epitaxial layer wherein the first groove extends to a surface of the first epitaxial layer without penetrating the first epitaxial layer;
depositing a third epitaxial layer of the second conductivity type on the second epitaxial layer and in the first groove, an impurity concentration of the third epitaxial layer lower than that of the second epitaxial layer;
selectively forming a first semiconductor region of the first conductivity type in the third epitaxial layer;
forming a trench penetrating, in the thickness direction, the first semiconductor region and the third epitaxial layer in the first groove and reaching the first epitaxial layer, a width of the trench narrower than that of the first groove;
forming a gate insulating film along an inner wall of the trench;
forming a gate electrode on the gate insulating film in the trench;
forming a first electrode on the first semiconductor region and electrically connected to the first semiconductor region and the third epitaxial layer; and
forming a second electrode electrically connected to a rear surface of the semiconductor substrate.

### Claim 9 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, comprising
forming a second groove after depositing the first epitaxial layer and before depositing the second epitaxial layer, the second groove formed in the first epitaxial layer at a predetermined depth in the thickness direction, a width of the second groove wider than that of the first groove, wherein
the second epitaxial layer is deposited in the second groove, and
the first groove is formed to penetrate, in the thickness direction, the second epitaxial layer in the second groove from a surface of the second epitaxial layer and reach the first epitaxial layer.

### Claim 10 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, comprising
forming a second semiconductor region of the second conductivity type after depositing the first epitaxial layer and before depositing the second epitaxial layer, the second semiconductor region formed in the first epitaxial layer, an impurity concentration of the second semiconductor region higher than that of the third epitaxial layer, wherein
the trench is formed so that at least a portion of a bottom of the trench reaches the second semiconductor region.

### Claim 11 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, wherein
the semiconductor material having a bandgap wider than that of silicon is silicon carbide.