# US 10,319,820 B2 · Semiconductor device having silicon carbide layer provided on silicon carbide substrate

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- Number: US 10,319,820 B2
- Document ID: US10319820B2
- Status: Granted
- Kind: B2
- Application number: 15/716,992
- Filed: 2017-09-27
- Published: 2018-04-26
- Granted: 2019-06-11
- Earliest claimed: 2016-10-21
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Akimasa Kinoshita; Yasuyuki Hoshi; Yasuhiko Oonishi; Yuichi Harada
- Web page: https://patentgrep.com/patent/US10319820B2

## CPC

- H10D 62/8325: {Silicon carbide}
- H10D 12/031: {of IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/159: {Shapes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 62/405: {Orientations of crystalline planes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon carbide semiconductor substrate of a first conductivity type;
a first silicon carbide layer of the first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration lower than that of the silicon carbide semiconductor substrate;
a first semiconductor region of a second conductivity type selectively provided in a surface layer on a first side of the first silicon carbide layer opposite a second side of the first silicon carbide layer facing the silicon carbide semiconductor substrate;
a second semiconductor region of the first conductivity type selectively provided in a surface layer on a first side of the first semiconductor region opposite a second side of the first semiconductor region facing toward the silicon carbide semiconductor substrate;
a third semiconductor region of the second conductivity type selectively provided in the surface layer on the first side of the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region;
a gate electrode provided, via a gate insulating film, on at least one portion of a surface of the first semiconductor region between the second semiconductor region and the first silicon carbide layer;
an interlayer insulating film provided on the gate electrode;
a source electrode provided on surfaces of the second semiconductor region and the third semiconductor region; and
a drain electrode provided on a rear surface of the silicon carbide semiconductor substrate, wherein
the third semiconductor region is thicker, in a depth direction, than the second semiconductor region, and
a width of a first side of the third semiconductor region facing the first semiconductor region is narrower than a width of a second side of the third semiconductor region facing the source electrode, wherein
a result of multiplying an impurity concentration of the first semiconductor region by a thickness of a region of the first semiconductor region between the third semiconductor region and the first silicon carbide layer is less than a result of multiplying the impurity concentration of the first silicon carbide layer by a thickness of a region of the first silicon carbide layer between the first semiconductor region and the silicon carbide semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the third semiconductor region is thicker, in the depth direction, than the first semiconductor region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
in a region of the first semiconductor region between the third semiconductor region and the first silicon carbide layer, an interface of the first semiconductor region and the first silicon carbide layer is closer to the source electrode than in other regions of the first semiconductor region and a thickness of the first semiconductor region, in the depth direction, is thinner than in the other regions of the first semiconductor region.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein
a width of the region of the first semiconductor region where the thickness is thinner than in other regions of the first semiconductor region is wider than a width of a region of the first silicon carbide layer between the first semiconductor region and an adjacent first semiconductor region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
a crystallographic plane index of the front surface of the silicon carbide semiconductor substrate is a plane parallel to or sloped within 10 degrees of (000-1).

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
a crystallographic plane index of the front surface of the silicon carbide semiconductor substrate is a plane parallel to or sloped within 10 degrees of (0001).

### Claim 7

A semiconductor device comprising:
a silicon carbide semiconductor substrate of a first conductivity type;
a first silicon carbide layer of the first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration lower than that of the silicon carbide semiconductor substrate;
a first semiconductor region of a second conductivity type selectively provided in a surface layer on a first side of the first silicon carbide layer opposite a second side of the first silicon carbide layer facing the silicon carbide semiconductor substrate;
a second semiconductor region of the second conductivity type selectively provided in surfaces of the first silicon carbide layer and first semiconductor region, the second semiconductor region having an impurity concentration lower than that of the first semiconductor region;
a third semiconductor region of the first conductivity type selectively provided in a surface layer on a first side of the second semiconductor region opposite a second side of the second semiconductor region facing toward the silicon carbide semiconductor substrate;
a fourth semiconductor region of the second conductivity type selectively provided in the surface layer on the first side of the second semiconductor region;
a fifth semiconductor region of the first conductivity type penetrating the second semiconductor region and reaching the first silicon carbide layer;
a gate electrode provided, via a gate insulating film, on at least one portion of a surface of the second semiconductor region between the third semiconductor region and the fifth semiconductor region;
an interlayer insulating film provided on the gate electrode;
a source electrode provided on surfaces of the third semiconductor region and the fourth semiconductor region; and
a drain electrode provided on a rear surface of the silicon carbide semiconductor substrate, wherein
the fourth semiconductor region is thicker, in a depth direction, than the second semiconductor region, and
a width of a first side of the fourth semiconductor region facing the first semiconductor region is narrower than a width of a second side of the fourth semiconductor region facing the source electrode.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein
a result of multiplying an impurity concentration of the first semiconductor region by a thickness of a region of the first semiconductor region between the fourth semiconductor region and the first silicon carbide layer is less than a result of multiplying the impurity concentration of the first silicon carbide layer by a thickness of a region of the first silicon carbide layer between the first semiconductor region and the silicon carbide semiconductor substrate.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein
an interface of the fourth semiconductor region and the first semiconductor region is closer to the first silicon carbide layer than an interface of the second semiconductor region and the first semiconductor region.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, wherein
in a region of the first semiconductor region between the fourth semiconductor region and the first silicon carbide layer, an interface of the first semiconductor region and the first silicon carbide layer is closer to the source electrode than in other regions of first semiconductor region and a thickness of the first semiconductor region, in the depth direction, is thinner than in the other regions of the first semiconductor region.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein
a width of the region of the first semiconductor region where the thickness is thinner than in the other regions of the first semiconductor region is wider than a width of a region of the first silicon carbide layer between the first semiconductor region and an adjacent first semiconductor region.

### Claim 12 (depends on 7)

The semiconductor device according to claim 7, wherein
a crystallographic plane index of the front surface of the silicon carbide semiconductor substrate is a plane parallel to or sloped within 10 degrees of (000-1).

### Claim 13 (depends on 7)

The semiconductor device according to claim 7, wherein
a crystallographic plane index of the front surface of the silicon carbide semiconductor substrate is a plane parallel to or sloped within 10 degrees of (0001).