# US 10,319,818 B2 · Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end

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- Number: US 10,319,818 B2
- Document ID: US10319818B2
- Status: Granted
- Kind: B2
- Application number: 15/797,774
- Filed: 2017-10-30
- Published: 2019-05-02
- Granted: 2019-06-11
- Earliest claimed: 2017-10-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Martin M. Frank; Takashi Ando; Xiao Sun; Jin Ping Han; Vijay Narayanan
- Web page: https://patentgrep.com/patent/US10319818B2

## CPC

- H10D 62/81: of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/689: {having ferroelectric layers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/82: of only field-effect components
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 72/00: Interconnections or connectors in packages
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

## Claims

### Claim 1

A method of forming a field-effect transistor (FET) device, the method comprising the steps of:
forming a shallow trench isolation (STI) region in a substrate separating a first active area of the substrate from a second active area of the substrate;
forming at least one ferroelectric FET (FeFET) on the substrate in the first active area having a ferroelectric material comprising a hafnium oxide (HfO2)-based material; and
forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric comprising the HfO2-based material,
wherein the method further comprises the steps of:
depositing the HfO2-based material onto the substrate in both the first active area and the second active area;
depositing a dielectric capping layer on the HfO2-based material in both the first active area and the second active area;
depositing a metal layer onto the dielectric capping layer in both the first active area and the second active area;
patterning the HfO2-based material, dielectric capping layer and the metal layer into the at least one FeFET on the substrate in the first active area; and
annealing both the at least one FeFET and the at least one logic FET.

### Claim 2 (depends on 1)

The method of claim 1, wherein the HfO2-based material is selected from the group consisting of: pure HfO2, hafnium zirconate (Hf˜0.5Zr˜0.5O2), doped HfO2, and combinations thereof.

### Claim 3 (depends on 2)

The method of claim 2, wherein the doped HfO2 comprises a dopant selected from the group consisting of: nitrogen (N), carbon (C), silicon (Si), aluminum (Al), lanthanum (La), gadolinium (Gd), yttrium (Y), scandium (Sc), strontium (Sr), and combinations thereof.

### Claim 4 (depends on 1)

The method of claim 1, wherein the dielectric capping layer comprises a material selected from the group consisting of: lanthanum oxide (La2O3), aluminum oxide (Al2O3), and combinations thereof.

### Claim 5 (depends on 1)

The method of claim 1, wherein the metal layer comprises a metal selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), and combinations thereof.

### Claim 6 (depends on 1)

The method of claim 1, further comprising the steps of:
covering the at least one FeFET with a mask;
depositing an additional dielectric capping layer onto the metal layer in the second active area;
depositing an additional metal layer onto the additional dielectric capping layer in the second active area; and
patterning the HfO2-based material, dielectric capping layer, the metal layer, the additional dielectric capping layer and the additional metal layer into the at least one logic FET on the substrate in the second active area.

### Claim 7 (depends on 6)

The method of claim 6, wherein the additional dielectric capping layer comprises a material selected from the group consisting of: La2O3, Al2O3 and combinations thereof.

### Claim 8 (depends on 6)

The method of claim 6, wherein the additional metal layer comprises a metal selected from the group consisting of: TiN, TaN, and combinations thereof.

### Claim 9 (depends on 1)

The method of claim 1, wherein the at least one FeFET and the at least one logic FET are annealed at a temperature of from about 800° C. to about 1200° C., and ranges therebetween.

### Claim 10 (depends on 1)

The method of claim 1, wherein the at least one FeFET and the at least one logic FET are annealed at a temperature of from about 1000° C. to about 1200° C., and ranges therebetween.