# US 10,319,815 B2 · Laterally diffused metal oxide semiconductor transistors for radio frequency power amplifiers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,815 B2 - Document ID: US10319815B2 - Status: Granted - Kind: B2 - Application number: 14/287,143 - Filed: 2014-05-26 - Published: 2014-09-11 - Granted: 2019-06-11 - Earliest claimed: 2011-10-31 - Assignees: NXP USA, Inc. - Applicants: Freescale Semiconductor, Inc. - Inventors: Xiaowei Ren; Robert P. Davidson; Mark A. DeTar - Web page: https://patentgrep.com/patent/US10319815B2 ## CPC - H10D 62/157: {Impurity concentrations or distributions} - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. ## Claims ### Claim 1 A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising: a substrate having a first surface and a second surface, wherein the first surface comprises an epitaxial layer, and wherein the first surface comprises a drain region, a source region, and a channel region for the LDMOS transistor; a first region formed from a first dopant of a first type having a first doping concentration, wherein the first region is a continuous region across the source region, the drain region, and the channel region, wherein the first region extends from the first surface into the substrate, stopping at a first depth below the first surface, and wherein the first depth is less than a depth of the epitaxial layer; a gate electrode over the channel region of the first surface of the substrate; a second dopant of a second type in the source region, the second dopant having a second doping concentration, wherein the second dopant extends from the first surface into the substrate, stopping at a second depth that is greater than the first depth, wherein the second dopant is laterally diffused under the gate electrode a predetermined distance, and wherein the second type is different than the first type; a third dopant of the first type in the drain region, the third dopant having a third doping concentration that is greater than the first doping concentration, wherein the third dopant extends from the first surface into the substrate, stopping at a third depth, the third depth being less than the first depth; a source implant in the source region; and a drain implant in the drain region. ### Claim 2 (depends on 1) The LDMOS transistor of claim 1, further comprising a sinker implant in the source region, wherein the sinker implant is used to provide a connection from the source region to the second surface of the substrate. ### Claim 3 (depends on 1) The LDMOS transistor of claim 1, wherein the first type is an N-type dopant and the second type is a P-type dopant. ### Claim 4 (depends on 1) The LDMOS transistor of claim 1, wherein the gate electrode is formed from polysilicon. ### Claim 5 (depends on 1) The LDMOS transistor of claim 1, wherein the epitaxial layer is lightly doped relative to a doping concentration of the substrate. ### Claim 6 (depends on 1) The LDMOS transistor of claim 1, wherein the second dopant is laterally diffused for substantially an entire length of the gate electrode. ### Claim 7 (depends on 1) The LDMOS transistor of claim 1, wherein the source implant is an N+ source implant and the drain implant is an N+ drain implant. ### Claim 8 (depends on 1) The LDMOS transistor of claim 1, wherein the third dopant has no lateral diffusion under the gate electrode. ### Claim 9 (depends on 1) The LDMOS transistor of claim 1, wherein a net doping concentration of the drain region is greater than either of the first doping concentration or the third doping concentration. ### Claim 10 A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising: a substrate having a first surface and a second surface, wherein the first surface comprises an epitaxial layer, and wherein the first surface comprises a drain region, a source region, and a channel region for the LDMOS transistor; a first region formed from a first N-type dopant having a first doping concentration, wherein the first region is a continuous region across the source region, the channel region, and the drain region, wherein the first region extends from the first surface into the substrate, stopping at a first depth below the first surface, and wherein the first depth is less than a depth of the epitaxial layer; a gate electrode over the channel region of the first surface of the substrate; a P-type dopant in the source region of the first surface, wherein the P-type dopant extends from the first surface into the substrate, stopping at a second depth that is greater than the first depth, the P-type dopant having a second doping concentration, wherein the P-type dopant laterally diffused under the gate electrode into the channel region a predetermined distance; a second N-type dopant in the drain region, the second N-type dopant having a third doping concentration that is greater than the first doping concentration, wherein the second N-type dopant extends from the first surface into the substrate, stopping at a third depth, the third depth being less than the first depth; an N+ source implant in the source region; and an N+ drain implant in the drain region. ### Claim 11 (depends on 10) The LDMOS transistor of claim 10, further comprising a sinker implant in the source region, wherein the sinker implant is used to provide a connection from the source region to the second surface of the substrate. ### Claim 12 (depends on 10) The LDMOS transistor of claim 10, wherein the gate electrode is formed from polysilicon. ### Claim 13 (depends on 10) The LDMOS transistor of claim 10, wherein the epitaxial layer is lightly doped relative to a doping concentration of the substrate. ### Claim 14 (depends on 10) The LDMOS transistor of claim 10, wherein the second dopant is laterally diffused for substantially an entire length of the gate electrode. ### Claim 15 (depends on 10) The LDMOS transistor of claim 10, wherein the third dopant further is implanted with minimal lateral diffusion under the gate electrode. ### Claim 16 A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising: a substrate having a surface, a source region, a drain region, and a channel region; a first region formed from a first implant of a first conductivity type, wherein the first region is a continuous region across the source region, the drain region, and the channel region, wherein the first region extends from the surface into the substrate, stopping at a first depth below the first surface; a gate electrode formed over the channel region; a second implant of a second conductivity type formed in the source region of the substrate, wherein the second implant extends from the surface into the substrate, stopping at a second depth that is greater than the first depth, and the second implant is laterally diffused under the gate electrode into the channel region a predetermined distance; and a third implant of the first conductivity type that extends from the surface into the substrate in the drain region of the substrate, wherein the third implant stops at a third depth, the third depth being less than the first depth. ### Claim 17 (depends on 16) The LDMOS transistor of claim 16, further comprising: an N+ source implant in the source region a first predetermined distance from the gate electrode; and an N+ drain implant in the drain region a second predetermined distance from the gate electrode, wherein the third implant is formed in the channel region from an edge of the gate electrode to the N+ drain implant. ### Claim 18 (depends on 16) The LDMOS transistor of claim 16, wherein the second implant is laterally diffused under the gate electrode for substantially an entire length of the gate electrode. ### Claim 19 (depends on 16) The LDMOS transistor of claim 16, wherein the first implant and the third implant each comprises an N-type dopant, and the second implant comprises a P-type dopant.