# US 10,319,813 B2 · Nanosheet CMOS transistors

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- Number: US 10,319,813 B2
- Document ID: US10319813B2
- Status: Granted
- Kind: B2
- Application number: 15/470,352
- Filed: 2017-03-27
- Published: 2018-09-27
- Granted: 2019-06-11
- Earliest claimed: 2017-03-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Zhenxing Bi; Kangguo Cheng; Juntao Li; Peng Xu
- Web page: https://patentgrep.com/patent/US10319813B2

## CPC

- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10W 90/00: Package configurations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Integrated chips and methods of forming the same include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.

## Claims

### Claim 1

An integrated chip, comprising:
a first semiconductor device in a first region, comprising:
a plurality of vertically aligned nanosheet channels formed from a first semiconductor material;
inner spacers formed directly between vertically adjacent nanosheet channels in the first device region; and
a source and drain region formed directly on sidewalls of each of the plurality of vertically aligned nanosheet channels; and
a second semiconductor device in a second region, comprising:
a plurality of vertically aligned nanosheet channels formed from a second semiconductor material, each of the nanosheets formed from the second semiconductor material having a same height as a respective nanosheet of the first material and being formed from nanosheet layers of the first semiconductor material by a condensation process;
inner spacers formed directly between vertically adjacent nanosheet channels in the second device region; and
a source and drain region formed directly on sidewalls of each of the plurality of vertically aligned nanosheet channels.

### Claim 2 (depends on 1)

The integrated chip of claim 1, wherein the first material is silicon and the second material is silicon germanium.

### Claim 3 (depends on 2)

The integrated chip of claim 2, wherein the second material has a germanium concentration of about 20%.

### Claim 4 (depends on 2)

The integrated chip of claim 2, wherein the first semiconductor device is an n-type field effect transistor and the second semiconductor device is a p-type field effect transistor.

### Claim 5 (depends on 1)

The integrated chip of claim 1, further comprising respective gate stacks formed directly on and around the plurality of vertically aligned nanosheet channels in each of the first and second semiconductor devices.

### Claim 6 (depends on 5)

The integrated chip of claim 5, wherein each gate stack comprises a respective gate dielectric layer and a respective gate conductor.

### Claim 7 (depends on 6)

The integrated chip of claim 6, wherein the gate dielectric layer of each gate stack is conformally formed on horizontal surfaces of the respective plurality of vertically aligned nanosheet channels and on vertical surfaces of the respective inner spacers.

### Claim 8 (depends on 5)

The integrated chip of claim 5, wherein the inner spacers of each device region are positioned between the respective gate stack and a respective source or drain region.

### Claim 9 (depends on 1)

The integrated chip of claim 1, wherein the plurality of vertically aligned nanosheet channels formed from the first semiconductor material and the plurality of vertically aligned nanosheet channels formed from the second semiconductor material have a same thickness.

### Claim 10 (depends on 9)

The integrated chip of claim 9, wherein the thickness of the plurality of vertically aligned nanosheet channels formed from the first semiconductor material and the plurality of vertically aligned nanosheet channels formed from the second semiconductor material have a thickness between about 5 nm and about 20 nm.

### Claim 11 (depends on 10)

The integrated chip of claim 10, wherein the thickness of the plurality of vertically aligned nanosheet channels formed from the first semiconductor material and the plurality of vertically aligned nanosheet channels formed from the second semiconductor material have a thickness between about 10 nm and about 12 nm.

### Claim 12 (depends on 11)

The integrated chip of claim 11, wherein a separation between vertically adjacent layers of the plurality of vertically aligned nanosheet channels formed from the first semiconductor material is between about 16 nm and about 22 nm.

### Claim 13 (depends on 1)

The integrated chip of claim 1, wherein a separation between vertically adjacent layers of the plurality of vertically aligned nanosheet channels formed from the first semiconductor material is between about 9 nm and about 32 nm.