# US 10,319,812 B2 · Self-aligned gate edge and local interconnect and method to fabricate same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,812 B2 - Document ID: US10319812B2 - Status: Granted - Kind: B2 - Application number: 15/789,315 - Filed: 2017-10-20 - Published: 2018-02-15 - Granted: 2019-06-11 - Earliest claimed: 2017-10-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Milton Clair Webb; Mark Bohr; Tahir Ghani; Szuya S. Liao - Web page: https://patentgrep.com/patent/US10319812B2 ## CPC - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/853: {comprising FinFETs} - H10W 20/0698: {Local interconnections} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10D 84/0135: {Manufacturing their gate conductors} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0188: {Manufacturing their isolation regions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure. ## Claims ### Claim 1 An integrated circuit structure, comprising: a first fin having a longest dimension along a first direction; a second fin having a longest dimension along the first direction; a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction; a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction; a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure having a length along the first direction greater than a length of the first gate structure and the second gate structure along the first direction; and a dielectric material laterally adjacent to and in contact with the gate edge isolation structure, and the dielectric material having a composition different than a composition of the gate edge isolation structure. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, and wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode. ### Claim 3 (depends on 2) The integrated circuit structure of claim 2, wherein the gate edge isolation structure is in contact with a gate dielectric layer of the first gate structure and with a gate dielectric layer of the second gate structure. ### Claim 4 (depends on 3) The integrated circuit structure of claim 3, wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and with a metal gate electrode layer of the second gate structure. ### Claim 5 (depends on 2) The integrated circuit structure of claim 2, wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric material, and wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric material. ### Claim 6 (depends on 1) The integrated circuit structure of claim 1, wherein the gate edge isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure. ### Claim 7 (depends on 6) The integrated circuit structure of claim 6, further comprising: a local interconnect disposed over a portion of the first gate structure, over a portion of the gate edge isolation structure, and over a portion of the second gate structure. ### Claim 8 (depends on 7) The integrated circuit structure of claim 7, wherein the local interconnect electrically couples the first gate structure to the second gate structure. ### Claim 9 (depends on 8) The integrated circuit structure of claim 8, further comprising: a gate contact on a portion of the local interconnect over the first gate structure, but not on a portion of the local interconnect over the second gate structure. ### Claim 10 (depends on 1) The integrated circuit structure of claim 1, wherein the gate edge isolation structure comprises silicon and nitrogen. ### Claim 11 A method of fabricating and integrated circuit structure, the method comprising: forming a first fin having a longest dimension along a first direction; forming a second fin having a longest dimension along the first direction; forming a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction; forming a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction; forming a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure having a length along the first direction greater than a length of the first gate structure and the second gate structure along the first direction; and forming a dielectric material laterally adjacent to and in contact with the gate edge isolation structure, and the dielectric material having a composition different than a composition of the gate edge isolation structure. ### Claim 12 (depends on 11) The method of claim 11, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, and wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode. ### Claim 13 (depends on 12) The method of claim 12, wherein the gate edge isolation structure is in contact with a gate dielectric layer of the first gate structure and with a gate dielectric layer of the second gate structure. ### Claim 14 (depends on 13) The method of claim 13, wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and with a metal gate electrode layer of the second gate structure. ### Claim 15 (depends on 12) The method of claim 12, wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric material, and wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric material. ### Claim 16 (depends on 11) The method of claim 11, wherein the gate edge isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure. ### Claim 17 (depends on 16) The method of claim 16, further comprising: forming a local interconnect disposed over a portion of the first gate structure, over a portion of the gate edge isolation structure, and over a portion of the second gate structure. ### Claim 18 (depends on 17) The method of claim 17, wherein the local interconnect electrically couples the first gate structure to the second gate structure. ### Claim 19 (depends on 18) The method of claim 18, further comprising: forming a gate contact on a portion of the local interconnect over the first gate structure, but not on a portion of the local interconnect over the second gate structure. ### Claim 20 (depends on 11) The method of claim 11, wherein the gate edge isolation structure comprises silicon and nitrogen. ### Claim 21 A method of fabricating an integrated circuit structure, the method comprising: forming a first fin comprising silicon, the first fin having a longest dimension along a first direction; forming a second fin comprising silicon, the second fin having a longest dimension along the first direction; forming an isolation material between the first fin and the second fin; forming a first gate structure over the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode; forming a second gate structure over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction, wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode; forming a gate edge isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate edge isolation structure over the isolation material; and forming a dielectric material laterally adjacent to the first and second gate structures along the first direction, the dielectric material laterally adjacent to the gate edge isolation structure along the first direction, and the dielectric material discrete from the gate edge isolation structure. ### Claim 22 (depends on 21) The method of claim 21, wherein the gate edge isolation structure comprises silicon and nitrogen. ### Claim 23 (depends on 21) The method of claim 21, wherein the dielectric material is in contact with the gate edge isolation structure. ### Claim 24 (depends on 21) The method of claim 21, wherein the gate edge isolation structure is in contact with a gate dielectric layer of the first gate structure and with a gate dielectric layer of the second gate structure. ### Claim 25 (depends on 24) The method of claim 24, wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and with a metal gate electrode layer of the second gate structure. ### Claim 26 (depends on 24) The method of claim 24, wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric material, and wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric material. ### Claim 27 (depends on 21) The method of claim 21, wherein the gate edge isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure. ### Claim 28 (depends on 27) The method of claim 27, further comprising: forming a local interconnect disposed over a portion of the first gate structure, over a portion of the gate edge isolation structure, and over a portion of the second gate structure. ### Claim 29 (depends on 28) The method of claim 28, wherein the local interconnect electrically couples the first gate structure to the second gate structure. ### Claim 30 (depends on 28) The method of claim 28, further comprising: forming a gate contact on a portion of the local interconnect over the first gate structure, but not on a portion of the local interconnect over the second gate structure.