# US 10,319,809 B2 · Structures to avoid floating resurf layer in high voltage lateral devices

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- Number: US 10,319,809 B2
- Document ID: US10319809B2
- Status: Granted
- Kind: B2
- Application number: 15/843,444
- Filed: 2017-12-15
- Published: 2018-04-19
- Granted: 2019-06-11
- Earliest claimed: 2015-02-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Yongxi Zhang; Philip L. Hower; John Lin; Guru Mathur; Scott G. Balster; Constantin Bulucea; Zachary K. Lee; Sameer P. Pendharkar
- Web page: https://patentgrep.com/patent/US10319809B2

## CPC

- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/516: {the thicknesses being non-uniform}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and
a vertical shunt of p-type semiconductor material disposed in the substrate, the vertical shunt extending vertically through an opening in the drain drift region, from the RESURF layer to the p-type semiconductor material below the drain drift region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×1016 cm−3 to 1×1017 cm−3.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a width of the vertical shunt is 3 microns to 8 microns.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a length of the vertical shunt is 3 microns to 10 microns.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the vertical shunt is laterally separated from the body by less than 3 microns.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, comprising a plurality of instances of the vertical shunt.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a resistance of the vertical shunt is 5000 to 50000 ohms.

### Claim 8

A semiconductor device, comprising:
a semiconductor substrate comprising p-type material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the semiconductor substrate; and
a drain drift region of n-type semiconductor material disposed in the semiconductor substrate, the drain drift region extending laterally to the body;
a doped layer of p-type semiconductor material disposed in the semiconductor substrate over at least a portion of the drain drift region, the doped layer extending from the drain drift region to a top surface of the semiconductor substrate; and
a vertical shunt of p-type semiconductor material disposed in the semiconductor substrate, the vertical shunt extending vertically through an opening in the drain drift region, between the doped layer and a p-type portion of the semiconductor substrate below the drain drift region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the doped layer is 1 micron to 5 microns thick, and has an average doping density of 1×1016 cm−3 to 1×1017 cm−3.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein a width of the vertical shunt is 3 microns to 8 microns.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein a length of the vertical shunt is 3 microns to 10 microns.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the vertical shunt is laterally separated from the body by less than 3 microns.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, comprising a plurality of instances of the vertical shunt.

### Claim 14

A semiconductor device, comprising:
a semiconductor substrate comprising p-type material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the semiconductor substrate;
a source region within the body;
a drain drift region of n-type semiconductor material disposed in the semiconductor substrate, the drain drift region extending laterally to the body; and
a gate extending over a portion of the body region and a portion of the drain drift region;
an oxide region at a portion of a top surface of the semiconductor substrate;
a doped layer of p-type semiconductor material disposed in the semiconductor substrate over at least a portion of the drain drift region, the doped layer extending from the drain drift region to the top surface of the semiconductor substrate under the oxide region;
a vertical shunt of p-type semiconductor material disposed in the semiconductor substrate, the vertical shunt extending vertically through an opening in the drain drift region, between the doped layer and a p-type portion of the semiconductor substrate below the drain drift region;
an n-type buried layer in the semiconductor substrate below the body; and
an n-type sinker in the semiconductor substrate, the n-type buried layer extending from the drain drift region to the n-type sinker, the n-type buried layer and n-type sinker isolating the body from a portion of the semiconductor substrate below the n-type buried layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the doped layer is 1 micron to 5 microns thick, and has an average doping density of 1×1016 cm−3 to 1×1017 cm−3.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a width of the vertical shunt is 3 microns to 8 microns.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a length of the vertical shunt is 3 microns to 10 microns.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the vertical shunt is laterally separated from the body by less than 3 microns.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, comprising a plurality of instances of the vertical shunt.