# US 10,319,786 B2 · Memory device

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- Number: US 10,319,786 B2
- Document ID: US10319786B2
- Status: Granted
- Kind: B2
- Application number: 15/909,579
- Filed: 2018-03-01
- Published: 2019-03-21
- Granted: 2019-06-11
- Earliest claimed: 2017-09-19
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Kei Sakamoto
- Web page: https://patentgrep.com/patent/US10319786B2

## CPC

- H10B 63/34: {of the vertical channel field-effect transistor type}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/841: {Electrodes}
- G11C 2213/71: Three dimensional array
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8822: {Sulfides, e.g. CuS}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device includes: a wiring; an electrode that includes a first portion provided on the wiring, and a second portion provided on the first portion; a first pillar and a second pillar that are provided inside the second portion; a first conductive layer that is provided below the first pillar; and a second conductive layer that is provided below the second pillar. The second portion includes a first conductive portion provided around the first pillar and including a first conductive material, a second conductive portion provided around the second pillar and containing the first conductive material, and a third conductive portion provided around the first and second conductive portions, containing a second conductive material, and electrically connected to the first portion and the first and second conductive portions. The first portion includes the second conductive material.

## Claims

### Claim 1

A memory device comprising:
a wiring;
an electrode that includes a first portion provided on the wiring and electrically connected to the wiring, and a second portion provided on and electrically connected to the first portion;
a first pillar provided inside the second portion;
a second pillar provided inside the second portion;
a first conductive layer provided below the first pillar, extending in a first direction, and electrically connected to the first pillar; and
a second conductive layer provided below the second pillar, extending in the first direction, and electrically connected to the second pillar,
wherein the second portion of the electrode includes:
a first conductive portion provided around the first pillar and comprising a first conductive material,
a second conductive portion provided around the second pillar and comprising the first conductive material, and
a third conductive portion provided around the first and second conductive portions, comprising a second conductive material, and electrically connected to the first and second conductive portions, and
wherein the first portion of the electrode comprises the second conductive material.

### Claim 2 (depends on 1)

The memory device according to claim 1,
wherein the second portion further includes:
a fourth conductive portion electrically connected to the first, second, and third conductive portions and comprising the first conductive material, and
a fifth conductive portion electrically connected to the first, second, and third conductive portions and comprising the first conductive material, and
wherein the first pillar, the second pillar, the first conductive portion, the second conductive portion, and the third conductive portion are provided between the fourth and fifth conductive portions.

### Claim 3 (depends on 2)

The memory device according to claim 2, further comprising:
a first gate insulating film provided between the first pillar and the first conductive portion; and
a second gate insulating film provided between the second pillar and the second conductive portion.

### Claim 4 (depends on 3)

The memory device according to claim 3,
wherein the first and second pillars comprise polycrystalline silicon.

### Claim 5 (depends on 4)

The memory device according to claim 4, further comprising:
a third conductive layer provided on the first pillar and extending in a second direction intersecting the first direction;
a fourth conductive layer provided on the second pillar and extending in the second direction; and
a variable resistance layer provided between the third and fourth conductive layers.

### Claim 6 (depends on 1)

The memory device according to claim 1, further comprising:
a first gate insulating film provided between the first pillar and the first conductive portion; and
a second gate insulating film provided between the second pillar and the second conductive portion.

### Claim 7 (depends on 1)

The memory device according to claim 1,
wherein the first and second pillars comprise polycrystalline silicon.

### Claim 8 (depends on 1)

The memory device according to claim 1, further comprising:
a third conductive layer provided on the first pillar and extending in a second direction intersecting the first direction;
a fourth conductive layer provided on the second pillar and extending in the second direction; and
a variable resistance layer provided between the third and fourth conductive layers.

### Claim 9 (depends on 1)

The memory device according to claim 1,
wherein the first conductive material comprises titanium nitride.

### Claim 10 (depends on 1)

The memory device according to claim 1,
wherein the second conductive material comprises tungsten.

### Claim 11

A method of manufacturing a memory device, comprising:
providing a wiring;
forming a first insulator on the wiring;
forming a first conductive layer extending in a first direction on the first insulator;
forming a second conductive layer extending in the first direction on the first insulator;
forming a first pillar electrically connected to the first conductive layer on the first conductive layer;
forming a second pillar electrically connected to the second conductive layer on the second conductive layer;
forming a second insulator around the first and second pillars;
forming a hole penetrating through the first and second insulators on the wiring to expose the wiring;
removing portions of the second insulator around the first and second pillars and around the hole;
forming a first conductive portion including a first conductive material around the first pillar;
forming a second conductive portion including the first conductive material around the second pillar; and
forming an electrode which includes a first portion and a second portion,
wherein the first portion is provided on the wiring and includes the second conductive material and is electrically connected to the wiring, and the second portion is provided on the first portion and includes a third conductive portion electrically connected to the first portion, includes the second conductive material, and is electrically connected to the first and second conductive portions,
wherein the electrode is formed such that the first and second pillars are provided inside the second portion of the electrode.

### Claim 12 (depends on 11)

The method according to claim 11,
wherein the first and second pillars comprise polycrystalline silicon.

### Claim 13 (depends on 11)

The method according to claim 11,
wherein the first conductive material comprises titanium nitride.

### Claim 14 (depends on 11)

The method according to claim 11,
wherein the second conductive material comprises tungsten.