# US 10,319,784 B2 · Semiconductor device including variable resistance memory device

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- Number: US 10,319,784 B2
- Document ID: US10319784B2
- Status: Granted
- Kind: B2
- Application number: 15/858,349
- Filed: 2017-12-29
- Published: 2018-12-06
- Granted: 2019-06-11
- Earliest claimed: 2017-06-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kil-ho Lee; Yoon-jong Song; Gwan-hyeob Koh
- Web page: https://patentgrep.com/patent/US10319784B2

## CPC

- H10B 61/22: {of the field-effect transistor [FET] type}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- G11C 11/1655: {Bit-line or column circuits}
- H10N 50/01: Manufacture or treatment
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate comprising a memory cell region and a logic region;
a variable resistance memory device on the memory cell region;
a logic device on the logic region;
a first horizontal bit line extending along a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device;
a second horizontal bit line extending along the surface of the substrate on the logic region and electrically connected to the logic device; and
a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the variable resistance memory device comprises a magnetic tunnel junction device.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein
the variable resistance memory device comprises a surface that is coplanar with a surface of the vertical bit line.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein
the first horizontal bit line is farther away from the substrate than the second horizontal bit line.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein
the vertical bit line is on the memory cell region and is disposed in a first insulating layer in which the variable resistance memory device is disposed, wherein the first insulating layer has a different dielectric constant than a second insulating layer in which the second horizontal bit line is disposed.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein
the vertical bit line is on the logic region and is disposed in a first insulating layer in which the variable resistance memory device is disposed, wherein the first insulating layer has a different dielectric constant than a second insulating layer in which the second horizontal bit line is disposed.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a memory cell peripheral region defined on the substrate and disposed between the memory cell region and the logic region, wherein the vertical bit line is on the memory cell peripheral region and is disposed in a first insulating layer in which the variable resistance memory device is disposed, wherein the first insulating layer has a different dielectric constant than a second insulating layer in which the second horizontal bit line is disposed.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first insulating layer surrounding the variable resistance memory device and a second insulating layer surrounding the second horizontal bit line, wherein a dielectric constant of the first insulating layer is greater than a dielectric constant of the second insulating layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein
the first insulating layer is on the second insulating layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein
a lower surface of the first insulating layer is coplanar with a lower surface of the variable resistance memory device.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising:
a third insulating layer on the first insulating layer, the third insulating layer surrounding the first horizontal bit line.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein
a dielectric constant of the first insulating layer is greater than a dielectric constant of the third insulating layer.

### Claim 13

A semiconductor device comprising:
a substrate wherein a memory cell region and a logic region are defined;
a first insulating layer on the substrate;
a second insulating layer disposed between the first insulating layer and the substrate and having a dielectric constant different from that of the first insulating layer;
a variable resistance memory device in the first insulating layer;
a first horizontal bit line connected to the variable resistance memory device and extending in a direction parallel to a surface of the substrate;
a second horizontal bit line in at least a portion of the second insulating layer and extending in a direction parallel to the surface of the substrate; and
a vertical bit line in at least a portion of the first insulating layer and extending in a direction perpendicular to the surface of the substrate and electrically connected to the first horizontal bit line and the second horizontal bit line.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein
a dielectric constant of the first insulating layer is greater than a dielectric constant of the second insulating layer.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein
an upper surface of the second horizontal bit line is coplanar with an upper surface of the second insulating layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein
the upper surface of the second insulating layer is coplanar with a lower surface of the variable resistance memory device.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein
the variable resistance memory device comprises a magnetic tunnel junction device.

### Claim 18

A semiconductor device comprising:
a substrate wherein a memory cell region and a logic region are defined;
a first insulating layer on the substrate;
a second insulating layer disposed between the first insulating layer and the substrate and having a dielectric constant different from that of the first insulating layer;
a variable resistance memory device in the first insulating layer on the memory cell region;
a logic device on the logic region;
a first horizontal bit line extending along a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device;
a second horizontal bit line in the second insulating layer and extending along the surface of the substrate on the logic region; and
a vertical bit line extending perpendicular to the surface of the substrate and electrically connected to the first horizontal bit line and the second horizontal bit line, wherein the variable resistance memory device is electrically connected to the logic device sequentially through the first horizontal bit line, the vertical bit line, and the second horizontal bit line.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein
a dielectric constant of the first insulating layer is greater than a dielectric constant of the second insulating layer.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein
the variable resistance memory device comprises a magnetic tunnel junction device.