# US 10,319,783 B2 · Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,783 B2
- Document ID: US10319783B2
- Status: Granted
- Kind: B2
- Application number: 15/824,448
- Filed: 2017-11-28
- Published: 2018-07-12
- Granted: 2019-06-11
- Earliest claimed: 2017-01-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Benjamin D. Briggs; Michael Rizzolo; Theodorus E. Standaert
- Web page: https://patentgrep.com/patent/US10319783B2

## CPC

- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10B 20/00: Read-only memory [ROM] devices
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/28: of insulating materials
- H10P 72/0418: {for etching}
- H10P 90/126: {by chemical etching}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

## Claims

### Claim 1

A method for forming a semiconductor structure, the method comprising:
depositing a barrier layer over an insulating layer incorporating magnetic random access memory (MRAM) regions;
forming magnetic tunnel junction (MTJ) stacks aligned with one or more of the MRAM regions;
forming a first dielectric layer covering the MTJ stacks;
forming a second dielectric layer over the first dielectric layer;
etching the second dielectric layer to form a first set of spacers adjacent the MTJ stacks;
removing exposed portions of the first dielectric layer to define a second set of L-shaped spacers directly contacting the first set of spacers; and
laterally etching sections of the barrier layer, after first and second spacer formation, to form electrodes directly contacting the MTJ stacks.

### Claim 2 (depends on 1)

The method of claim 1, further comprising patterning and encapsulating the MTJ stacks before forming the first and second set of spacers.

### Claim 3 (depends on 1)

The method of claim 1, further comprising having the electrodes directly contact the MTJ stacks above the barrier layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising having the electrodes directly contact the MRAM regions below the barrier layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first dielectric layer is a nitride layer and the second dielectric layer is an oxide layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second dielectric layer has a thickness greater than a thickness of the first dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the electrodes contact an entire upper surface of their respective MRAM regions.

### Claim 8 (depends on 1)

The method of claim 1, wherein the electrodes are recessed from their respective first and second sets of spacers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the barrier layer is a tantalum nitride (TaN) layer.

### Claim 10 (depends on 1)

The method of claim 1, further comprising creating airgaps via dielectric deposition with pinch-off to reduce capacitive coupling.

### Claim 11

A semiconductor structure comprising:
a barrier layer deposited over an insulating layer incorporating magnetic random access memory (MRAM) regions;
magnetic tunnel junction (MTJ) stacks aligned with one or more of the MRAM regions;
a first dielectric layer covering the MTJ stacks;
a second dielectric layer formed over the first dielectric layer;
a first set of spacers formed adjacent the MTJ stacks by etching the second dielectric layer; and
a second set of L-shaped spacers defined by removing exposed portions of the first dielectric layer;
wherein sections of the barrier layer are laterally etched, after first and second spacer formation, to form electrodes directly contacting the MTJ stacks.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the MTJ stacks are patterned and encapsulated before forming the first and second set of spacers.

### Claim 13 (depends on 11)

The structure of claim 11, wherein the electrodes directly contact the MTJ stacks above the barrier layer.

### Claim 14 (depends on 11)

The structure of claim 11, wherein the electrodes directly contact the MRAM regions below the barrier layer.

### Claim 15 (depends on 11)

The structure of claim 11, wherein the first dielectric layer is a nitride layer and the second dielectric layer is an oxide layer.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the second dielectric layer has a thickness greater than a thickness of the first dielectric layer.

### Claim 17 (depends on 11)

The structure of claim 11, wherein the electrodes contact an entire upper surface of their respective MRAM regions.

### Claim 18 (depends on 11)

The structure of claim 11, wherein the electrodes are recessed from their respective first and second sets of spacers.

### Claim 19 (depends on 11)

The structure of claim 11, wherein the barrier layer is a tantalum nitride (TaN) layer.

### Claim 20 (depends on 11)

The structure of claim 11, wherein airgaps are created via dielectric deposition with pinch-off to reduce capacitive coupling.