# US 10,319,778 B2 · Light receiving element and light receiving device

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- Number: US 10,319,778 B2
- Document ID: US10319778B2
- Status: Granted
- Kind: B2
- Application number: 15/961,064
- Filed: 2018-04-24
- Published: 2018-11-29
- Granted: 2019-06-11
- Earliest claimed: 2017-05-26
- Assignees: Sumitomo Electric Industries, Ltd.
- Applicants: Sumitomo Electric Industries, Ltd.
- Inventors: Daisuke Kimura; Hiroshi Inada
- Web page: https://patentgrep.com/patent/US10319778B2

## CPC

- H10F 39/1843: {of the hybrid type}
- H10F 30/223: the potential barrier being a PIN barrier
- H10F 39/021: {of image sensors having active layers comprising only Group III-V materials, e.g. GaAs, AlGaAs or InP}
- H10F 39/811: {Interconnections}
- H10F 71/127: {The active layers comprising only Group III-V materials, e.g. GaAs or InP}
- H10F 77/124: comprising only Group III-V materials, e.g. GaAs
- H10F 77/146: {Superlattices; Multiple quantum well structures}
- H10F 77/147: {Shapes of bodies}
- H10F 77/206: {for devices having potential barriers}
- H10F 77/306: {for devices having potential barriers}
- H10F 77/933: {for devices having potential barriers}
- H10W 72/30: Die-attach connectors
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01255: {by using masks}
- H10W 72/013: {of die-attach connectors}
- H10W 72/01338: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/332: {Plan-view shape, i.e. in top view}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/348: {Top-view layouts, e.g. mirror arrays}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/90: Bond pads, in general
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A light receiving element includes: a semiconductor layer including a first layer, a light absorbing layer, a second layer, and a third layer, the semiconductor layer having a plurality of mesas, a terrace, and a groove; a first electrode provided on the mesas and electrically connected to the third layer; a first bump provided on the first electrode and electrically connected to the first electrode; a second electrode provided on a portion extending from the terrace to an inner side of the groove and electrically connected to the first layer; and a second bump larger than the first bump, is provided on the terrace, and is electrically connected to the second electrode, wherein the mesas and the terrace include the semiconductor layer, the groove extends to the first layer, and the second electrode is in contact with the first layer on an inner side of the groove.

## Claims

### Claim 1

A light receiving element comprising:
a semiconductor substrate formed with a compound semiconductor,
a semiconductor layer including: a first layer that is provided on the semiconductor substrate and is of a first conductivity type; a light absorbing layer provided on the first layer; a second layer that is provided on the light absorbing layer and is of a second conductivity type; and a third layer that is provided on the second layer and is of the second conductivity type, the semiconductor layer forming a plurality of mesas, a terrace, and a groove at a portion of the semiconductor substrate extending from a middle portion thereof toward an outer peripheral portion thereof;
a first electrode that is provided on at least one of the mesas, and is electrically connected to the third layer,
a first bump that is provided on the first electrode, and is electrically connected to the first electrode;
a second electrode that is provided on a portion extending from the terrace to an inner side of the groove, and is electrically connected to the first layer; and
a second bump that has a larger size than the first bump, that is provided on the terrace, and that is electrically connected to the second electrode, wherein
the mesas and the terrace include the first layer, the light absorbing layer, the second layer, and the third layer,
the groove extends to the first layer, and
the second electrode is in contact with the first layer on an inner side of the groove.

### Claim 2 (depends on 1)

The light receiving element according to claim 1, wherein an area of the second bump in a direction in which the semiconductor substrate extends is at least four times larger than an area of the first bump.

### Claim 3 (depends on 1)

The light receiving element according to claim 1, wherein the second bump is provided on a portion of the semiconductor substrate extending from the terrace to an inner side of the groove, and covers a surface of the second electrode.

### Claim 4 (depends on 1)

The light receiving element according to claim 1, further comprising
an insulating film that covers respective upper and side surfaces of the mesas and the terrace, wherein
the insulating film has a first opening above the mesas, and a second opening on an inner side of the groove,
the first electrode is in contact with the third layer exposed through the first opening, and
the second electrode is in contact with the first layer exposed through the second opening.

### Claim 5 (depends on 1)

The light receiving element according to claim 1, wherein the second bump has a ring-like shape, and surrounds a region of the semiconductor layer, the plurality of mesas being provided in the region.

### Claim 6 (depends on 1)

The light receiving element according to claim 1, further comprising a plurality of second bumps, wherein
each second bump has a shape that extends along at least two sides of the semiconductor substrate, and
the second bumps are at a distance from one another and form a square, the second bumps being located at respective four corners of the square.

### Claim 7 (depends on 1)

The light receiving element according to claim 1, wherein the second bump is formed by four columnar bumps, the four columnar bumps forming a square and each of the columner bumps being located at a respective corner of the square.

### Claim 8 (depends on 1)

The light receiving element according to claim 1, wherein the semiconductor substrate is formed with gallium antimonide.

### Claim 9 (depends on 1)

The light receiving element according to claim 1, wherein
the first layer is an n-type superlattice layer, and
the second layer is a p-type superlattice layer.

### Claim 10

A light receiving device comprising:
a silicon substrate, and
a light receiving element electrically connected to the silicon substrate, the light receiving element including:
a semiconductor substrate formed with a compound semiconductor;
a semiconductor layer including: a first layer that is provided on the semiconductor substrate and is of a first conductivity type; a light absorbing layer provided on the first layer; a second layer that is provided on the light absorbing layer and is of a second conductivity type; and a third layer that is provided on the second layer and is of the second conductivity type, the semiconductor layer forming a plurality of mesas, a terrace, and a groove at a portion of the semiconductor substrate extending from a middle portion thereof toward an outer peripheral portion thereof;
a first electrode that is provided on at least one of the mesas, and is electrically connected to the third layer;
a first bump that is provided on the first electrode, and is electrically connected to the first electrode;
a second electrode that is provided on a portion extending from the terrace to an inner side of the groove, and is electrically connected to the first layer; and
a second bump that has a larger size than the first bump, that is provided on the terrace, and that is electrically connected to the second electrode, wherein
the mesas and the terrace include the first layer, the light absorbing layer, the second layer, and the third layer,
the groove extends to the first layer, and
the second electrode is in contact with the first layer on an inner side of the groove, and wherein
the first bump and the second bump of the light receiving element electrically connect the light receiving element to the silicon substrate.