# US 10,319,752 B2 · Array substrate and method for making same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,752 B2 - Document ID: US10319752B2 - Status: Granted - Kind: B2 - Application number: 15/252,900 - Filed: 2016-08-31 - Published: 2017-03-23 - Granted: 2019-06-11 - Earliest claimed: 2015-09-18 - Assignees: Hon Hai Precision Industry Co., Ltd. - Applicants: Hon Hai Precision Industry Co., Ltd. - Inventors: Yi-Chun Kao; Hsin-Hua Lin - Web page: https://patentgrep.com/patent/US10319752B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10D 30/0312: {characterised by the gate electrodes} - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/6729: {characterised by the electrodes} - H10D 30/6731: {Top-gate only TFTs} - H10D 30/674: {characterised by the active materials} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 86/021: {of multiple TFTs} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/427: {having different thicknesses of the semiconductor bodies in different TFTs} - H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 30/204: {into Group IV semiconductors} - H10P 30/21: {of electrically active species} - H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions} - H10D 30/6732: {Bottom-gate only TFTs} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10K 59/1213: {the pixel elements being TFTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole. ## Claims ### Claim 1 An array substrate comprising: a substrate; a first insulator layer formed on the substrate; a second insulator layer formed on the first insulator layer; a third insulator layer formed on the second insulator layer; a first TFT formed on the substrate, the first TFT comprising a first channel layer on the substrate, a first gate electrode on the first insulator layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode on the third insulator layer; a storage capacitance layer formed on the substrate; and a second TFT formed on the substrate, the second TFT comprising a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode, the second source electrode and the second drain electrode on the third insulator layer; the first insulator layer covering the first channel layer and the storage capacitance layer; the second insulator layer covering the first gate electrode and the second gate electrode; wherein the first channel layer and the storage capacitance layer are made of a semiconducting material containing polycrystalline silicon; the second channel layer is made of a semiconducting material containing metal oxide; the third insulator layer covers the second channel layer; a second source hole and a second drain hole are defined to extend through the third insulator layer and overlap the second channel layer; a portion of the third insulator layer between the second drain hole and the second source hole defines a protection portion; wherein a first source hole and a first drain hole are defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the first channel layer; the first source electrode extends into the first source hole to electrically couple to the first channel layer; the first drain electrode extends into the first drain hole to electrically couple to the first channel layer; a storage capacitance hole is defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the storage capacitance layer; the second source electrode extends into the second source hole to electrically couple to the second channel layer; the second drain electrode extends into the second drain hole to electrically couple to the second channel layer; and the second drain electrode also extends into the storage capacitance hole to electrically couple to the storage capacitance layer. ### Claim 2 (depends on 1) The array substrate of claim 1, wherein: the first channel layer is at least partially doped with P-type ions and comprises a non-doped portion not doped with P-type ions, two lightly P-type ion doped portions, and two heavily P-type ion doped portions; the two lightly P-type ion doped portions are located at opposite sides of the non-doped portion; each heavily P-type ion doped portion is located at a side of one lightly P-type ion doped portion away from the non-doped portion; and the heavily P-type ion doped portion has a P-type ion concentration greater than that of the lightly P-type ion doped portion. ### Claim 3 (depends on 1) The array substrate of claim 1, wherein the first channel layer is doped with N-type ions and comprises an ultra-lightly-doped portion, two lightly-doped portions, and two heavily-doped portions; the two lightly-doped portions are located at opposite sides of the ultra-lightly-doped portion; each heavily-doped portion is located at a side of one lightly-doped portion away from the ultra-lightly-doped portion; the heavily-doped portion has a N-type ion concentration greater than that of the lightly-doped portion; and the lightly-doped portion has a N-type ion concentration greater than that of the ultra-lightly-doped portion. ### Claim 4 (depends on 1) The array substrate of claim 1, wherein the array substrate further comprises a fourth insulator layer formed on the third insulator layer, a fifth insulator layer formed on the fourth insulator layer, a first electrode layer formed on the fourth insulator layer, and a second electrode layer formed on the fifth insulator layer; the first electrode layer is covered by the fifth insulator layer; the fourth insulator layer defines a first connecting hole corresponding to the second drain electrode and passing through the fourth insulator layer; the fifth insulator layer defines a second connecting hole corresponding to the first connecting hole and passing through the fifth insulator layer and the fourth insulator layer; the second electrode layer extends into the second connecting hole to electrically couple to the second drain electrode. ### Claim 5 (depends on 1) The array substrate of claim 1, wherein the array substrate further comprises a third TFT formed on the substrate, the third TFT comprises a third channel layer on the substrate, a third gate electrode on the first insulator layer, and a third source electrode and a third drain electrode on the third insulator layer and electrically coupled to the third channel layer; the third channel layer is made of a semiconducting material containing polycrystalline silicon doped with P-type ions and comprises a ultra-lightly-doped portion, two lightly-doped portions, and two heavily-doped portions; the two lightly-doped portions are located at opposite sides of the ultra-lightly-doped portion; each heavily-doped portion is located at a side of one lightly-doped portion away from the ultra lightly-doped portion; the heavily-doped portion has a P-type ion concentration greater than that of the lightly-doped portion; and the lightly-doped portion has a P-type ion concentration greater than that of the ultra-lightly-doped portion. ### Claim 6 An array substrate comprising: a substrate, the substrate defining a display area and a peripheral area around the display area; a first insulator layer, the first insulator layer formed on the substrate and extending from the display area to the peripheral area; a second insulator layer, the second insulator layer formed on the first insulator layer and extending from the display area to the peripheral area; a third insulator layer, the third insulator layer formed on the second insulator layer and extending from the display area to the peripheral area; a first TFT, the first TFT formed on the substrate and positioned in the peripheral area, the first TFT comprising a first channel layer on the substrate, a first gate electrode on the first insulator layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode on the third insulator layer; a storage capacitance layer formed on the substrate; a second TFT, the second TFT formed on the substrate and positioned in the display area, the second TFT comprising a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode on the third insulator layer; and a third TFT, the third TFT formed on the substrate and positioned in the display area, the third TFT comprising a third gate electrode on the first insulator layer, a third channel layer on the second insulator layer, a third source electrode, and a third drain electrode, the third source electrode and the third drain electrode on the third insulator layer and electrically coupled to the third channel layer; the first insulator layer covering the first channel layer and the storage capacitance layer; the second insulator layer covering the first gate electrode, the second gate electrode, and the third electrode; wherein the first channel layer and the storage capacitance layer are made of a semiconducting material containing polycrystalline silicon; the second channel layer and the third channel layer are made of a semiconducting material containing metal oxide; the third insulator layer covers the second channel layer; a second source hole and a second drain hole are defined to overlap the second channel layer and extend through the third insulator layer; a third source hole and a third drain hole are defined to extend through the third insulator layer and overlap the third channel layer; a portion of the third insulator layer between the second drain hole and the second source hole defines a first protection portion; a portion of the third insulator layer between the third drain hole and the third source hole defines a second protection portion; wherein a first source hole and a first drain hole are defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the first channel layer; the first source electrode extends into the first source hole to electrically couple to the first channel layer; the first drain electrode extends into the first drain hole to electrically couple to the first channel layer; a storage capacitance hole is defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the storage capacitance layer; the second source electrode extends into the second source hole to electrically couple to the second channel layer; the second drain electrode extends into the second drain hole to electrically couple to the second channel layer; and the second drain electrode also extends into the storage capacitance hole to electrically couple to the storage capacitance layer. ### Claim 7 (depends on 6) The array substrate of claim 6, wherein the first channel layer is at least partially doped with P-type ions and comprises a non-doped portion doped not doped with P-type ion, two lightly P-type ion doped portions, and two heavily P-type ion doped portions; the two lightly P-type ion doped portions are located at opposite sides of the non-doped portion; each heavily P-type ion doped portion is located at a side of one lightly P-type ion doped portion away from the non-doped portion; and the heavily P-type ion doped portion has a P-type ion concentration greater than that of the lightly P-type ion doped portion. ### Claim 8 (depends on 6) The array substrate of claim 6, wherein the first channel layer is doped with N-type ions and comprises an ultra-lightly-doped portion, two lightly-doped portions, and two heavily-doped portions; the two lightly-doped portions are located at opposite sides of the ultra-lightly-doped portion; each heavily-doped portion is located at a side of one lightly-doped portion away from the ultra-lightly-doped portion; the heavily-doped portion has a N-type ion concentration greater than that of the lightly-doped portion; and the lightly-doped portion has a N-type ion concentration greater than that of the ultra-lightly-doped portion. ### Claim 9 (depends on 6) The array substrate of claim 6, wherein the array substrate further comprises a fourth insulator layer on the third insulator layer, an anode layer on the fourth insulator layer, and a pixel electrode layer on the fourth insulator layer; the pixel electrode layer partially covers the anode layer; the fourth insulator layer defines an anode hole corresponding to the second drain electrode and passing through the fourth insulator layer; the anode layer extends into the anode hole to electrically couple to the second drain electrode. ### Claim 10 (depends on 6) The array substrate of claim 6, wherein the array substrate further comprises a fourth TFT formed on the substrate and positioned in the peripheral area, the fourth TFT comprising a fourth channel layer on the substrate, a fourth gate electrode on the first insulator layer, and a fourth source electrode and a fourth drain electrode on the third insulator layer and electrically coupled to the fourth channel layer; the fourth channel layer is made of a semiconducting material containing polycrystalline silicon doped with P-type ions and comprises a ultra-lightly-doped portion, two lightly-doped portions, and two heavily-doped portions; the two lightly-doped portions are located at opposite sides of the ultra-lightly-doped portion; each heavily-doped portion is located at a side of one lightly-doped portion away from the ultra lightly-doped portion; the heavily-doped portion has a P-type ion concentration greater than that of the lightly-doped portion; and the lightly-doped portion has a P-type ion concentration greater than that of the ultra-lightly-doped portion.